pci/aw2/saa7146.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*****************************************************************************
0003  *
0004  * Copyright (C) 2008 Cedric Bregardis <cedric.bregardis@free.fr> and
0005  * Jean-Christian Hassler <jhassler@free.fr>
0006  *
0007  * This file is part of the Audiowerk2 ALSA driver
0008  *
0009  *****************************************************************************/
0010
0011 /* SAA7146 registers */
0012 #define PCI_BT_A    0x4C
0013 #define IICTFR      0x8C
0014 #define IICSTA      0x90
0015 #define BaseA1_in   0x94
0016 #define ProtA1_in   0x98
0017 #define PageA1_in   0x9C
0018 #define BaseA1_out  0xA0
0019 #define ProtA1_out  0xA4
0020 #define PageA1_out  0xA8
0021 #define BaseA2_in   0xAC
0022 #define ProtA2_in   0xB0
0023 #define PageA2_in   0xB4
0024 #define BaseA2_out  0xB8
0025 #define ProtA2_out  0xBC
0026 #define PageA2_out  0xC0
0027 #define IER     0xDC
0028 #define GPIO_CTRL   0xE0
0029 #define ACON1       0xF4
0030 #define ACON2       0xF8
0031 #define MC1     0xFC
0032 #define MC2     0x100
0033 #define ISR     0x10C
0034 #define PSR     0x110
0035 #define SSR     0x114
0036 #define PCI_ADP1    0x12C
0037 #define PCI_ADP2    0x130
0038 #define PCI_ADP3    0x134
0039 #define PCI_ADP4    0x138
0040 #define LEVEL_REP   0x140
0041 #define FB_BUFFER1  0x144
0042 #define FB_BUFFER2  0x148
0043 #define TSL1        0x180
0044 #define TSL2        0x1C0
0045
0046 #define ME  (1UL << 11)
0047 #define LIMIT   (1UL << 4)
0048 #define PV  (1UL << 3)
0049
0050 /* PSR/ISR/IER */
0051 #define PPEF        (1UL << 31)
0052 #define PABO        (1UL << 30)
0053 #define IIC_S       (1UL << 17)
0054 #define IIC_E       (1UL << 16)
0055 #define A2_in       (1UL << 15)
0056 #define A2_out      (1UL << 14)
0057 #define A1_in       (1UL << 13)
0058 #define A1_out      (1UL << 12)
0059 #define AFOU        (1UL << 11)
0060 #define PIN3        (1UL << 6)
0061 #define PIN2        (1UL << 5)
0062 #define PIN1        (1UL << 4)
0063 #define PIN0        (1UL << 3)
0064 #define ECS     (1UL << 2)
0065 #define EC3S        (1UL << 1)
0066 #define EC0S        (1UL << 0)
0067
0068 /* SSR */
0069 #define PRQ     (1UL << 31)
0070 #define PMA     (1UL << 30)
0071 #define IIC_EA      (1UL << 21)
0072 #define IIC_EW      (1UL << 20)
0073 #define IIC_ER      (1UL << 19)
0074 #define IIC_EL      (1UL << 18)
0075 #define IIC_EF      (1UL << 17)
0076 #define AF2_in      (1UL << 10)
0077 #define AF2_out     (1UL << 9)
0078 #define AF1_in      (1UL << 8)
0079 #define AF1_out     (1UL << 7)
0080 #define EC5S        (1UL << 3)
0081 #define EC4S        (1UL << 2)
0082 #define EC2S        (1UL << 1)
0083 #define EC1S        (1UL << 0)
0084
0085 /* PCI_BT_A */
0086 #define BurstA1_in  (1UL << 26)
0087 #define ThreshA1_in (1UL << 24)
0088 #define BurstA1_out (1UL << 18)
0089 #define ThreshA1_out    (1UL << 16)
0090 #define BurstA2_in  (1UL << 10)
0091 #define ThreshA2_in (1UL << 8)
0092 #define BurstA2_out (1UL << 2)
0093 #define ThreshA2_out    (1UL << 0)
0094
0095 /* MC1 */
0096 #define MRST_N      (1UL << 15)
0097 #define EAP     (1UL << 9)
0098 #define EI2C        (1UL << 8)
0099 #define TR_E_A2_OUT (1UL << 3)
0100 #define TR_E_A2_IN  (1UL << 2)
0101 #define TR_E_A1_OUT (1UL << 1)
0102 #define TR_E_A1_IN  (1UL << 0)
0103
0104 /* MC2 */
0105 #define UPLD_IIC    (1UL << 0)
0106
0107 /* ACON1 */
0108 #define AUDIO_MODE  (1UL << 29)
0109 #define MAXLEVEL    (1UL << 22)
0110 #define A1_SWAP     (1UL << 21)
0111 #define A2_SWAP     (1UL << 20)
0112 #define WS0_CTRL    (1UL << 18)
0113 #define WS0_SYNC    (1UL << 16)
0114 #define WS1_CTRL    (1UL << 14)
0115 #define WS1_SYNC    (1UL << 12)
0116 #define WS2_CTRL    (1UL << 10)
0117 #define WS2_SYNC    (1UL << 8)
0118 #define WS3_CTRL    (1UL << 6)
0119 #define WS3_SYNC    (1UL << 4)
0120 #define WS4_CTRL    (1UL << 2)
0121 #define WS4_SYNC    (1UL << 0)
0122
0123 /* ACON2 */
0124 #define A1_CLKSRC   (1UL << 27)
0125 #define A2_CLKSRC   (1UL << 22)
0126 #define INVERT_BCLK1    (1UL << 21)
0127 #define INVERT_BCLK2    (1UL << 20)
0128 #define BCLK1_OEN   (1UL << 19)
0129 #define BCLK2_OEN   (1UL << 18)
0130
0131 /* IICSTA */
0132 #define IICCC       (1UL << 8)
0133 #define ABORT       (1UL << 7)
0134 #define SPERR       (1UL << 6)
0135 #define APERR       (1UL << 5)
0136 #define DTERR       (1UL << 4)
0137 #define DRERR       (1UL << 3)
0138 #define AL      (1UL << 2)
0139 #define ERR     (1UL << 1)
0140 #define BUSY        (1UL << 0)
0141
0142 /* IICTFR */
0143 #define BYTE2       (1UL << 24)
0144 #define BYTE1       (1UL << 16)
0145 #define BYTE0       (1UL << 8)
0146 #define ATRR2       (1UL << 6)
0147 #define ATRR1       (1UL << 4)
0148 #define ATRR0       (1UL << 2)
0149 #define ERR     (1UL << 1)
0150 #define BUSY        (1UL << 0)
0151
0152 #define START   3
0153 #define CONT    2
0154 #define STOP    1
0155 #define NOP 0