pci/aw2/aw2-tsl.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*****************************************************************************
0003  *
0004  * Copyright (C) 2008 Cedric Bregardis <cedric.bregardis@free.fr> and
0005  * Jean-Christian Hassler <jhassler@free.fr>
0006  * Copyright 1998 Emagic Soft- und Hardware GmbH
0007  * Copyright 2002 Martijn Sipkema
0008  *
0009  * This file is part of the Audiowerk2 ALSA driver
0010  *
0011  *****************************************************************************/
0012
0013 #define TSL_WS0     (1UL << 31)
0014 #define TSL_WS1     (1UL << 30)
0015 #define TSL_WS2     (1UL << 29)
0016 #define TSL_WS3     (1UL << 28)
0017 #define TSL_WS4     (1UL << 27)
0018 #define TSL_DIS_A1  (1UL << 24)
0019 #define TSL_SDW_A1  (1UL << 23)
0020 #define TSL_SIB_A1  (1UL << 22)
0021 #define TSL_SF_A1   (1UL << 21)
0022 #define TSL_LF_A1   (1UL << 20)
0023 #define TSL_BSEL_A1 (1UL << 17)
0024 #define TSL_DOD_A1  (1UL << 15)
0025 #define TSL_LOW_A1  (1UL << 14)
0026 #define TSL_DIS_A2  (1UL << 11)
0027 #define TSL_SDW_A2  (1UL << 10)
0028 #define TSL_SIB_A2  (1UL << 9)
0029 #define TSL_SF_A2   (1UL << 8)
0030 #define TSL_LF_A2   (1UL << 7)
0031 #define TSL_BSEL_A2 (1UL << 4)
0032 #define TSL_DOD_A2  (1UL << 2)
0033 #define TSL_LOW_A2  (1UL << 1)
0034 #define TSL_EOS     (1UL << 0)
0035
0036     /* Audiowerk8 hardware setup: */
0037     /*      WS0, SD4, TSL1  - Analog/ digital in */
0038     /*      WS1, SD0, TSL1  - Analog out #1, digital out */
0039     /*      WS2, SD2, TSL1  - Analog out #2 */
0040     /*      WS3, SD1, TSL2  - Analog out #3 */
0041     /*      WS4, SD3, TSL2  - Analog out #4 */
0042
0043     /* Audiowerk8 timing: */
0044     /*      Timeslot:     | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | ... */
0045
0046     /*      A1_INPUT: */
0047     /*      SD4:          <_ADC-L_>-------<_ADC-R_>-------< */
0048     /*      WS0:          _______________/---------------\_ */
0049
0050     /*      A1_OUTPUT: */
0051     /*      SD0:          <_1-L___>-------<_1-R___>-------< */
0052     /*      WS1:          _______________/---------------\_ */
0053     /*      SD2:          >-------<_2-L___>-------<_2-R___> */
0054     /*      WS2:          -------\_______________/--------- */
0055
0056     /*      A2_OUTPUT: */
0057     /*      SD1:          <_3-L___>-------<_3-R___>-------< */
0058     /*      WS3:          _______________/---------------\_ */
0059     /*      SD3:          >-------<_4-L___>-------<_4-R___> */
0060     /*      WS4:          -------\_______________/--------- */
0061
0062 static const int tsl1[8] = {
0063     1 * TSL_SDW_A1 | 3 * TSL_BSEL_A1 |
0064     0 * TSL_DIS_A1 | 0 * TSL_DOD_A1 | TSL_LF_A1,
0065
0066     1 * TSL_SDW_A1 | 2 * TSL_BSEL_A1 |
0067     0 * TSL_DIS_A1 | 0 * TSL_DOD_A1,
0068
0069     0 * TSL_SDW_A1 | 3 * TSL_BSEL_A1 |
0070     0 * TSL_DIS_A1 | 0 * TSL_DOD_A1,
0071
0072     0 * TSL_SDW_A1 | 2 * TSL_BSEL_A1 |
0073     0 * TSL_DIS_A1 | 0 * TSL_DOD_A1,
0074
0075     1 * TSL_SDW_A1 | 1 * TSL_BSEL_A1 |
0076     0 * TSL_DIS_A1 | 0 * TSL_DOD_A1 | TSL_WS1 | TSL_WS0,
0077
0078     1 * TSL_SDW_A1 | 0 * TSL_BSEL_A1 |
0079     0 * TSL_DIS_A1 | 0 * TSL_DOD_A1 | TSL_WS1 | TSL_WS0,
0080
0081     0 * TSL_SDW_A1 | 1 * TSL_BSEL_A1 |
0082     0 * TSL_DIS_A1 | 0 * TSL_DOD_A1 | TSL_WS1 | TSL_WS0,
0083
0084     0 * TSL_SDW_A1 | 0 * TSL_BSEL_A1 | 0 * TSL_DIS_A1 |
0085     0 * TSL_DOD_A1 | TSL_WS1 | TSL_WS0 | TSL_SF_A1 | TSL_EOS,
0086 };
0087
0088 static const int tsl2[8] = {
0089     0 * TSL_SDW_A2 | 3 * TSL_BSEL_A2 | 2 * TSL_DOD_A2 | TSL_LF_A2,
0090     0 * TSL_SDW_A2 | 2 * TSL_BSEL_A2 | 2 * TSL_DOD_A2,
0091     0 * TSL_SDW_A2 | 3 * TSL_BSEL_A2 | 2 * TSL_DOD_A2,
0092     0 * TSL_SDW_A2 | 2 * TSL_BSEL_A2 | 2 * TSL_DOD_A2,
0093     0 * TSL_SDW_A2 | 1 * TSL_BSEL_A2 | 2 * TSL_DOD_A2 | TSL_WS2,
0094     0 * TSL_SDW_A2 | 0 * TSL_BSEL_A2 | 2 * TSL_DOD_A2 | TSL_WS2,
0095     0 * TSL_SDW_A2 | 1 * TSL_BSEL_A2 | 2 * TSL_DOD_A2 | TSL_WS2,
0096     0 * TSL_SDW_A2 | 0 * TSL_BSEL_A2 | 2 * TSL_DOD_A2 | TSL_WS2 | TSL_EOS
0097 };