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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *   ALSA driver for ATI IXP 150/200/250/300 AC97 controllers
0004  *
0005  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
0006  */
0007 
0008 #include <linux/io.h>
0009 #include <linux/delay.h>
0010 #include <linux/interrupt.h>
0011 #include <linux/init.h>
0012 #include <linux/pci.h>
0013 #include <linux/slab.h>
0014 #include <linux/module.h>
0015 #include <linux/mutex.h>
0016 #include <sound/core.h>
0017 #include <sound/pcm.h>
0018 #include <sound/pcm_params.h>
0019 #include <sound/info.h>
0020 #include <sound/ac97_codec.h>
0021 #include <sound/initval.h>
0022 
0023 MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
0024 MODULE_DESCRIPTION("ATI IXP AC97 controller");
0025 MODULE_LICENSE("GPL");
0026 
0027 static int index = SNDRV_DEFAULT_IDX1;  /* Index 0-MAX */
0028 static char *id = SNDRV_DEFAULT_STR1;   /* ID for this card */
0029 static int ac97_clock = 48000;
0030 static char *ac97_quirk;
0031 static bool spdif_aclink = 1;
0032 static int ac97_codec = -1;
0033 
0034 module_param(index, int, 0444);
0035 MODULE_PARM_DESC(index, "Index value for ATI IXP controller.");
0036 module_param(id, charp, 0444);
0037 MODULE_PARM_DESC(id, "ID string for ATI IXP controller.");
0038 module_param(ac97_clock, int, 0444);
0039 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (default 48000Hz).");
0040 module_param(ac97_quirk, charp, 0444);
0041 MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
0042 module_param(ac97_codec, int, 0444);
0043 MODULE_PARM_DESC(ac97_codec, "Specify codec instead of probing.");
0044 module_param(spdif_aclink, bool, 0444);
0045 MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link.");
0046 
0047 /* just for backward compatibility */
0048 static bool enable;
0049 module_param(enable, bool, 0444);
0050 
0051 
0052 /*
0053  */
0054 
0055 #define ATI_REG_ISR         0x00    /* interrupt source */
0056 #define  ATI_REG_ISR_IN_XRUN        (1U<<0)
0057 #define  ATI_REG_ISR_IN_STATUS      (1U<<1)
0058 #define  ATI_REG_ISR_OUT_XRUN       (1U<<2)
0059 #define  ATI_REG_ISR_OUT_STATUS     (1U<<3)
0060 #define  ATI_REG_ISR_SPDF_XRUN      (1U<<4)
0061 #define  ATI_REG_ISR_SPDF_STATUS    (1U<<5)
0062 #define  ATI_REG_ISR_PHYS_INTR      (1U<<8)
0063 #define  ATI_REG_ISR_PHYS_MISMATCH  (1U<<9)
0064 #define  ATI_REG_ISR_CODEC0_NOT_READY   (1U<<10)
0065 #define  ATI_REG_ISR_CODEC1_NOT_READY   (1U<<11)
0066 #define  ATI_REG_ISR_CODEC2_NOT_READY   (1U<<12)
0067 #define  ATI_REG_ISR_NEW_FRAME      (1U<<13)
0068 
0069 #define ATI_REG_IER         0x04    /* interrupt enable */
0070 #define  ATI_REG_IER_IN_XRUN_EN     (1U<<0)
0071 #define  ATI_REG_IER_IO_STATUS_EN   (1U<<1)
0072 #define  ATI_REG_IER_OUT_XRUN_EN    (1U<<2)
0073 #define  ATI_REG_IER_OUT_XRUN_COND  (1U<<3)
0074 #define  ATI_REG_IER_SPDF_XRUN_EN   (1U<<4)
0075 #define  ATI_REG_IER_SPDF_STATUS_EN (1U<<5)
0076 #define  ATI_REG_IER_PHYS_INTR_EN   (1U<<8)
0077 #define  ATI_REG_IER_PHYS_MISMATCH_EN   (1U<<9)
0078 #define  ATI_REG_IER_CODEC0_INTR_EN (1U<<10)
0079 #define  ATI_REG_IER_CODEC1_INTR_EN (1U<<11)
0080 #define  ATI_REG_IER_CODEC2_INTR_EN (1U<<12)
0081 #define  ATI_REG_IER_NEW_FRAME_EN   (1U<<13)    /* (RO */
0082 #define  ATI_REG_IER_SET_BUS_BUSY   (1U<<14)    /* (WO) audio is running */
0083 
0084 #define ATI_REG_CMD         0x08    /* command */
0085 #define  ATI_REG_CMD_POWERDOWN      (1U<<0)
0086 #define  ATI_REG_CMD_RECEIVE_EN     (1U<<1)
0087 #define  ATI_REG_CMD_SEND_EN        (1U<<2)
0088 #define  ATI_REG_CMD_STATUS_MEM     (1U<<3)
0089 #define  ATI_REG_CMD_SPDF_OUT_EN    (1U<<4)
0090 #define  ATI_REG_CMD_SPDF_STATUS_MEM    (1U<<5)
0091 #define  ATI_REG_CMD_SPDF_THRESHOLD (3U<<6)
0092 #define  ATI_REG_CMD_SPDF_THRESHOLD_SHIFT   6
0093 #define  ATI_REG_CMD_IN_DMA_EN      (1U<<8)
0094 #define  ATI_REG_CMD_OUT_DMA_EN     (1U<<9)
0095 #define  ATI_REG_CMD_SPDF_DMA_EN    (1U<<10)
0096 #define  ATI_REG_CMD_SPDF_OUT_STOPPED   (1U<<11)
0097 #define  ATI_REG_CMD_SPDF_CONFIG_MASK   (7U<<12)
0098 #define   ATI_REG_CMD_SPDF_CONFIG_34    (1U<<12)
0099 #define   ATI_REG_CMD_SPDF_CONFIG_78    (2U<<12)
0100 #define   ATI_REG_CMD_SPDF_CONFIG_69    (3U<<12)
0101 #define   ATI_REG_CMD_SPDF_CONFIG_01    (4U<<12)
0102 #define  ATI_REG_CMD_INTERLEAVE_SPDF    (1U<<16)
0103 #define  ATI_REG_CMD_AUDIO_PRESENT  (1U<<20)
0104 #define  ATI_REG_CMD_INTERLEAVE_IN  (1U<<21)
0105 #define  ATI_REG_CMD_INTERLEAVE_OUT (1U<<22)
0106 #define  ATI_REG_CMD_LOOPBACK_EN    (1U<<23)
0107 #define  ATI_REG_CMD_PACKED_DIS     (1U<<24)
0108 #define  ATI_REG_CMD_BURST_EN       (1U<<25)
0109 #define  ATI_REG_CMD_PANIC_EN       (1U<<26)
0110 #define  ATI_REG_CMD_MODEM_PRESENT  (1U<<27)
0111 #define  ATI_REG_CMD_ACLINK_ACTIVE  (1U<<28)
0112 #define  ATI_REG_CMD_AC_SOFT_RESET  (1U<<29)
0113 #define  ATI_REG_CMD_AC_SYNC        (1U<<30)
0114 #define  ATI_REG_CMD_AC_RESET       (1U<<31)
0115 
0116 #define ATI_REG_PHYS_OUT_ADDR       0x0c
0117 #define  ATI_REG_PHYS_OUT_CODEC_MASK    (3U<<0)
0118 #define  ATI_REG_PHYS_OUT_RW        (1U<<2)
0119 #define  ATI_REG_PHYS_OUT_ADDR_EN   (1U<<8)
0120 #define  ATI_REG_PHYS_OUT_ADDR_SHIFT    9
0121 #define  ATI_REG_PHYS_OUT_DATA_SHIFT    16
0122 
0123 #define ATI_REG_PHYS_IN_ADDR        0x10
0124 #define  ATI_REG_PHYS_IN_READ_FLAG  (1U<<8)
0125 #define  ATI_REG_PHYS_IN_ADDR_SHIFT 9
0126 #define  ATI_REG_PHYS_IN_DATA_SHIFT 16
0127 
0128 #define ATI_REG_SLOTREQ         0x14
0129 
0130 #define ATI_REG_COUNTER         0x18
0131 #define  ATI_REG_COUNTER_SLOT       (3U<<0) /* slot # */
0132 #define  ATI_REG_COUNTER_BITCLOCK   (31U<<8)
0133 
0134 #define ATI_REG_IN_FIFO_THRESHOLD   0x1c
0135 
0136 #define ATI_REG_IN_DMA_LINKPTR      0x20
0137 #define ATI_REG_IN_DMA_DT_START     0x24    /* RO */
0138 #define ATI_REG_IN_DMA_DT_NEXT      0x28    /* RO */
0139 #define ATI_REG_IN_DMA_DT_CUR       0x2c    /* RO */
0140 #define ATI_REG_IN_DMA_DT_SIZE      0x30
0141 
0142 #define ATI_REG_OUT_DMA_SLOT        0x34
0143 #define  ATI_REG_OUT_DMA_SLOT_BIT(x)    (1U << ((x) - 3))
0144 #define  ATI_REG_OUT_DMA_SLOT_MASK  0x1ff
0145 #define  ATI_REG_OUT_DMA_THRESHOLD_MASK 0xf800
0146 #define  ATI_REG_OUT_DMA_THRESHOLD_SHIFT    11
0147 
0148 #define ATI_REG_OUT_DMA_LINKPTR     0x38
0149 #define ATI_REG_OUT_DMA_DT_START    0x3c    /* RO */
0150 #define ATI_REG_OUT_DMA_DT_NEXT     0x40    /* RO */
0151 #define ATI_REG_OUT_DMA_DT_CUR      0x44    /* RO */
0152 #define ATI_REG_OUT_DMA_DT_SIZE     0x48
0153 
0154 #define ATI_REG_SPDF_CMD        0x4c
0155 #define  ATI_REG_SPDF_CMD_LFSR      (1U<<4)
0156 #define  ATI_REG_SPDF_CMD_SINGLE_CH (1U<<5)
0157 #define  ATI_REG_SPDF_CMD_LFSR_ACC  (0xff<<8)   /* RO */
0158 
0159 #define ATI_REG_SPDF_DMA_LINKPTR    0x50
0160 #define ATI_REG_SPDF_DMA_DT_START   0x54    /* RO */
0161 #define ATI_REG_SPDF_DMA_DT_NEXT    0x58    /* RO */
0162 #define ATI_REG_SPDF_DMA_DT_CUR     0x5c    /* RO */
0163 #define ATI_REG_SPDF_DMA_DT_SIZE    0x60
0164 
0165 #define ATI_REG_MODEM_MIRROR        0x7c
0166 #define ATI_REG_AUDIO_MIRROR        0x80
0167 
0168 #define ATI_REG_6CH_REORDER     0x84    /* reorder slots for 6ch */
0169 #define  ATI_REG_6CH_REORDER_EN     (1U<<0) /* 3,4,7,8,6,9 -> 3,4,6,9,7,8 */
0170 
0171 #define ATI_REG_FIFO_FLUSH      0x88
0172 #define  ATI_REG_FIFO_OUT_FLUSH     (1U<<0)
0173 #define  ATI_REG_FIFO_IN_FLUSH      (1U<<1)
0174 
0175 /* LINKPTR */
0176 #define  ATI_REG_LINKPTR_EN     (1U<<0)
0177 
0178 /* [INT|OUT|SPDIF]_DMA_DT_SIZE */
0179 #define  ATI_REG_DMA_DT_SIZE        (0xffffU<<0)
0180 #define  ATI_REG_DMA_FIFO_USED      (0x1fU<<16)
0181 #define  ATI_REG_DMA_FIFO_FREE      (0x1fU<<21)
0182 #define  ATI_REG_DMA_STATE      (7U<<26)
0183 
0184 
0185 #define ATI_MAX_DESCRIPTORS 256 /* max number of descriptor packets */
0186 
0187 
0188 struct atiixp;
0189 
0190 /*
0191  * DMA packate descriptor
0192  */
0193 
0194 struct atiixp_dma_desc {
0195     __le32 addr;    /* DMA buffer address */
0196     u16 status; /* status bits */
0197     u16 size;   /* size of the packet in dwords */
0198     __le32 next;    /* address of the next packet descriptor */
0199 };
0200 
0201 /*
0202  * stream enum
0203  */
0204 enum { ATI_DMA_PLAYBACK, ATI_DMA_CAPTURE, ATI_DMA_SPDIF, NUM_ATI_DMAS }; /* DMAs */
0205 enum { ATI_PCM_OUT, ATI_PCM_IN, ATI_PCM_SPDIF, NUM_ATI_PCMS }; /* AC97 pcm slots */
0206 enum { ATI_PCMDEV_ANALOG, ATI_PCMDEV_DIGITAL, NUM_ATI_PCMDEVS }; /* pcm devices */
0207 
0208 #define NUM_ATI_CODECS  3
0209 
0210 
0211 /*
0212  * constants and callbacks for each DMA type
0213  */
0214 struct atiixp_dma_ops {
0215     int type;           /* ATI_DMA_XXX */
0216     unsigned int llp_offset;    /* LINKPTR offset */
0217     unsigned int dt_cur;        /* DT_CUR offset */
0218     /* called from open callback */
0219     void (*enable_dma)(struct atiixp *chip, int on);
0220     /* called from trigger (START/STOP) */
0221     void (*enable_transfer)(struct atiixp *chip, int on);
0222     /* called from trigger (STOP only) */
0223     void (*flush_dma)(struct atiixp *chip);
0224 };
0225 
0226 /*
0227  * DMA stream
0228  */
0229 struct atiixp_dma {
0230     const struct atiixp_dma_ops *ops;
0231     struct snd_dma_buffer desc_buf;
0232     struct snd_pcm_substream *substream;    /* assigned PCM substream */
0233     unsigned int buf_addr, buf_bytes;   /* DMA buffer address, bytes */
0234     unsigned int period_bytes, periods;
0235     int opened;
0236     int running;
0237     int suspended;
0238     int pcm_open_flag;
0239     int ac97_pcm_type;  /* index # of ac97_pcm to access, -1 = not used */
0240     unsigned int saved_curptr;
0241 };
0242 
0243 /*
0244  * ATI IXP chip
0245  */
0246 struct atiixp {
0247     struct snd_card *card;
0248     struct pci_dev *pci;
0249 
0250     unsigned long addr;
0251     void __iomem *remap_addr;
0252     int irq;
0253     
0254     struct snd_ac97_bus *ac97_bus;
0255     struct snd_ac97 *ac97[NUM_ATI_CODECS];
0256 
0257     spinlock_t reg_lock;
0258 
0259     struct atiixp_dma dmas[NUM_ATI_DMAS];
0260     struct ac97_pcm *pcms[NUM_ATI_PCMS];
0261     struct snd_pcm *pcmdevs[NUM_ATI_PCMDEVS];
0262 
0263     int max_channels;       /* max. channels for PCM out */
0264 
0265     unsigned int codec_not_ready_bits;  /* for codec detection */
0266 
0267     int spdif_over_aclink;      /* passed from the module option */
0268     struct mutex open_mutex;    /* playback open mutex */
0269 };
0270 
0271 
0272 /*
0273  */
0274 static const struct pci_device_id snd_atiixp_ids[] = {
0275     { PCI_VDEVICE(ATI, 0x4341), 0 }, /* SB200 */
0276     { PCI_VDEVICE(ATI, 0x4361), 0 }, /* SB300 */
0277     { PCI_VDEVICE(ATI, 0x4370), 0 }, /* SB400 */
0278     { PCI_VDEVICE(ATI, 0x4382), 0 }, /* SB600 */
0279     { 0, }
0280 };
0281 
0282 MODULE_DEVICE_TABLE(pci, snd_atiixp_ids);
0283 
0284 static const struct snd_pci_quirk atiixp_quirks[] = {
0285     SND_PCI_QUIRK(0x105b, 0x0c81, "Foxconn RC4107MA-RS2", 0),
0286     SND_PCI_QUIRK(0x15bd, 0x3100, "DFI RS482", 0),
0287     { } /* terminator */
0288 };
0289 
0290 /*
0291  * lowlevel functions
0292  */
0293 
0294 /*
0295  * update the bits of the given register.
0296  * return 1 if the bits changed.
0297  */
0298 static int snd_atiixp_update_bits(struct atiixp *chip, unsigned int reg,
0299                  unsigned int mask, unsigned int value)
0300 {
0301     void __iomem *addr = chip->remap_addr + reg;
0302     unsigned int data, old_data;
0303     old_data = data = readl(addr);
0304     data &= ~mask;
0305     data |= value;
0306     if (old_data == data)
0307         return 0;
0308     writel(data, addr);
0309     return 1;
0310 }
0311 
0312 /*
0313  * macros for easy use
0314  */
0315 #define atiixp_write(chip,reg,value) \
0316     writel(value, chip->remap_addr + ATI_REG_##reg)
0317 #define atiixp_read(chip,reg) \
0318     readl(chip->remap_addr + ATI_REG_##reg)
0319 #define atiixp_update(chip,reg,mask,val) \
0320     snd_atiixp_update_bits(chip, ATI_REG_##reg, mask, val)
0321 
0322 /*
0323  * handling DMA packets
0324  *
0325  * we allocate a linear buffer for the DMA, and split it to  each packet.
0326  * in a future version, a scatter-gather buffer should be implemented.
0327  */
0328 
0329 #define ATI_DESC_LIST_SIZE \
0330     PAGE_ALIGN(ATI_MAX_DESCRIPTORS * sizeof(struct atiixp_dma_desc))
0331 
0332 /*
0333  * build packets ring for the given buffer size.
0334  *
0335  * IXP handles the buffer descriptors, which are connected as a linked
0336  * list.  although we can change the list dynamically, in this version,
0337  * a static RING of buffer descriptors is used.
0338  *
0339  * the ring is built in this function, and is set up to the hardware. 
0340  */
0341 static int atiixp_build_dma_packets(struct atiixp *chip, struct atiixp_dma *dma,
0342                     struct snd_pcm_substream *substream,
0343                     unsigned int periods,
0344                     unsigned int period_bytes)
0345 {
0346     unsigned int i;
0347     u32 addr, desc_addr;
0348     unsigned long flags;
0349 
0350     if (periods > ATI_MAX_DESCRIPTORS)
0351         return -ENOMEM;
0352 
0353     if (dma->desc_buf.area == NULL) {
0354         if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
0355                     &chip->pci->dev,
0356                     ATI_DESC_LIST_SIZE,
0357                     &dma->desc_buf) < 0)
0358             return -ENOMEM;
0359         dma->period_bytes = dma->periods = 0; /* clear */
0360     }
0361 
0362     if (dma->periods == periods && dma->period_bytes == period_bytes)
0363         return 0;
0364 
0365     /* reset DMA before changing the descriptor table */
0366     spin_lock_irqsave(&chip->reg_lock, flags);
0367     writel(0, chip->remap_addr + dma->ops->llp_offset);
0368     dma->ops->enable_dma(chip, 0);
0369     dma->ops->enable_dma(chip, 1);
0370     spin_unlock_irqrestore(&chip->reg_lock, flags);
0371 
0372     /* fill the entries */
0373     addr = (u32)substream->runtime->dma_addr;
0374     desc_addr = (u32)dma->desc_buf.addr;
0375     for (i = 0; i < periods; i++) {
0376         struct atiixp_dma_desc *desc;
0377         desc = &((struct atiixp_dma_desc *)dma->desc_buf.area)[i];
0378         desc->addr = cpu_to_le32(addr);
0379         desc->status = 0;
0380         desc->size = period_bytes >> 2; /* in dwords */
0381         desc_addr += sizeof(struct atiixp_dma_desc);
0382         if (i == periods - 1)
0383             desc->next = cpu_to_le32((u32)dma->desc_buf.addr);
0384         else
0385             desc->next = cpu_to_le32(desc_addr);
0386         addr += period_bytes;
0387     }
0388 
0389     writel((u32)dma->desc_buf.addr | ATI_REG_LINKPTR_EN,
0390            chip->remap_addr + dma->ops->llp_offset);
0391 
0392     dma->period_bytes = period_bytes;
0393     dma->periods = periods;
0394 
0395     return 0;
0396 }
0397 
0398 /*
0399  * remove the ring buffer and release it if assigned
0400  */
0401 static void atiixp_clear_dma_packets(struct atiixp *chip, struct atiixp_dma *dma,
0402                      struct snd_pcm_substream *substream)
0403 {
0404     if (dma->desc_buf.area) {
0405         writel(0, chip->remap_addr + dma->ops->llp_offset);
0406         snd_dma_free_pages(&dma->desc_buf);
0407         dma->desc_buf.area = NULL;
0408     }
0409 }
0410 
0411 /*
0412  * AC97 interface
0413  */
0414 static int snd_atiixp_acquire_codec(struct atiixp *chip)
0415 {
0416     int timeout = 1000;
0417 
0418     while (atiixp_read(chip, PHYS_OUT_ADDR) & ATI_REG_PHYS_OUT_ADDR_EN) {
0419         if (! timeout--) {
0420             dev_warn(chip->card->dev, "codec acquire timeout\n");
0421             return -EBUSY;
0422         }
0423         udelay(1);
0424     }
0425     return 0;
0426 }
0427 
0428 static unsigned short snd_atiixp_codec_read(struct atiixp *chip, unsigned short codec, unsigned short reg)
0429 {
0430     unsigned int data;
0431     int timeout;
0432 
0433     if (snd_atiixp_acquire_codec(chip) < 0)
0434         return 0xffff;
0435     data = (reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) |
0436         ATI_REG_PHYS_OUT_ADDR_EN |
0437         ATI_REG_PHYS_OUT_RW |
0438         codec;
0439     atiixp_write(chip, PHYS_OUT_ADDR, data);
0440     if (snd_atiixp_acquire_codec(chip) < 0)
0441         return 0xffff;
0442     timeout = 1000;
0443     do {
0444         data = atiixp_read(chip, PHYS_IN_ADDR);
0445         if (data & ATI_REG_PHYS_IN_READ_FLAG)
0446             return data >> ATI_REG_PHYS_IN_DATA_SHIFT;
0447         udelay(1);
0448     } while (--timeout);
0449     /* time out may happen during reset */
0450     if (reg < 0x7c)
0451         dev_warn(chip->card->dev, "codec read timeout (reg %x)\n", reg);
0452     return 0xffff;
0453 }
0454 
0455 
0456 static void snd_atiixp_codec_write(struct atiixp *chip, unsigned short codec,
0457                    unsigned short reg, unsigned short val)
0458 {
0459     unsigned int data;
0460     
0461     if (snd_atiixp_acquire_codec(chip) < 0)
0462         return;
0463     data = ((unsigned int)val << ATI_REG_PHYS_OUT_DATA_SHIFT) |
0464         ((unsigned int)reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) |
0465         ATI_REG_PHYS_OUT_ADDR_EN | codec;
0466     atiixp_write(chip, PHYS_OUT_ADDR, data);
0467 }
0468 
0469 
0470 static unsigned short snd_atiixp_ac97_read(struct snd_ac97 *ac97,
0471                        unsigned short reg)
0472 {
0473     struct atiixp *chip = ac97->private_data;
0474     return snd_atiixp_codec_read(chip, ac97->num, reg);
0475     
0476 }
0477 
0478 static void snd_atiixp_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
0479                   unsigned short val)
0480 {
0481     struct atiixp *chip = ac97->private_data;
0482     snd_atiixp_codec_write(chip, ac97->num, reg, val);
0483 }
0484 
0485 /*
0486  * reset AC link
0487  */
0488 static int snd_atiixp_aclink_reset(struct atiixp *chip)
0489 {
0490     int timeout;
0491 
0492     /* reset powerdoewn */
0493     if (atiixp_update(chip, CMD, ATI_REG_CMD_POWERDOWN, 0))
0494         udelay(10);
0495 
0496     /* perform a software reset */
0497     atiixp_update(chip, CMD, ATI_REG_CMD_AC_SOFT_RESET, ATI_REG_CMD_AC_SOFT_RESET);
0498     atiixp_read(chip, CMD);
0499     udelay(10);
0500     atiixp_update(chip, CMD, ATI_REG_CMD_AC_SOFT_RESET, 0);
0501     
0502     timeout = 10;
0503     while (! (atiixp_read(chip, CMD) & ATI_REG_CMD_ACLINK_ACTIVE)) {
0504         /* do a hard reset */
0505         atiixp_update(chip, CMD, ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET,
0506                   ATI_REG_CMD_AC_SYNC);
0507         atiixp_read(chip, CMD);
0508         mdelay(1);
0509         atiixp_update(chip, CMD, ATI_REG_CMD_AC_RESET, ATI_REG_CMD_AC_RESET);
0510         if (!--timeout) {
0511             dev_err(chip->card->dev, "codec reset timeout\n");
0512             break;
0513         }
0514     }
0515 
0516     /* deassert RESET and assert SYNC to make sure */
0517     atiixp_update(chip, CMD, ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET,
0518               ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET);
0519 
0520     return 0;
0521 }
0522 
0523 #ifdef CONFIG_PM_SLEEP
0524 static int snd_atiixp_aclink_down(struct atiixp *chip)
0525 {
0526     // if (atiixp_read(chip, MODEM_MIRROR) & 0x1) /* modem running, too? */
0527     //  return -EBUSY;
0528     atiixp_update(chip, CMD,
0529              ATI_REG_CMD_POWERDOWN | ATI_REG_CMD_AC_RESET,
0530              ATI_REG_CMD_POWERDOWN);
0531     return 0;
0532 }
0533 #endif
0534 
0535 /*
0536  * auto-detection of codecs
0537  *
0538  * the IXP chip can generate interrupts for the non-existing codecs.
0539  * NEW_FRAME interrupt is used to make sure that the interrupt is generated
0540  * even if all three codecs are connected.
0541  */
0542 
0543 #define ALL_CODEC_NOT_READY \
0544         (ATI_REG_ISR_CODEC0_NOT_READY |\
0545          ATI_REG_ISR_CODEC1_NOT_READY |\
0546          ATI_REG_ISR_CODEC2_NOT_READY)
0547 #define CODEC_CHECK_BITS (ALL_CODEC_NOT_READY|ATI_REG_ISR_NEW_FRAME)
0548 
0549 static int ac97_probing_bugs(struct pci_dev *pci)
0550 {
0551     const struct snd_pci_quirk *q;
0552 
0553     q = snd_pci_quirk_lookup(pci, atiixp_quirks);
0554     if (q) {
0555         dev_dbg(&pci->dev, "atiixp quirk for %s.  Forcing codec %d\n",
0556             snd_pci_quirk_name(q), q->value);
0557         return q->value;
0558     }
0559     /* this hardware doesn't need workarounds.  Probe for codec */
0560     return -1;
0561 }
0562 
0563 static int snd_atiixp_codec_detect(struct atiixp *chip)
0564 {
0565     int timeout;
0566 
0567     chip->codec_not_ready_bits = 0;
0568     if (ac97_codec == -1)
0569         ac97_codec = ac97_probing_bugs(chip->pci);
0570     if (ac97_codec >= 0) {
0571         chip->codec_not_ready_bits |= 
0572             CODEC_CHECK_BITS ^ (1 << (ac97_codec + 10));
0573         return 0;
0574     }
0575 
0576     atiixp_write(chip, IER, CODEC_CHECK_BITS);
0577     /* wait for the interrupts */
0578     timeout = 50;
0579     while (timeout-- > 0) {
0580         mdelay(1);
0581         if (chip->codec_not_ready_bits)
0582             break;
0583     }
0584     atiixp_write(chip, IER, 0); /* disable irqs */
0585 
0586     if ((chip->codec_not_ready_bits & ALL_CODEC_NOT_READY) == ALL_CODEC_NOT_READY) {
0587         dev_err(chip->card->dev, "no codec detected!\n");
0588         return -ENXIO;
0589     }
0590     return 0;
0591 }
0592 
0593 
0594 /*
0595  * enable DMA and irqs
0596  */
0597 static int snd_atiixp_chip_start(struct atiixp *chip)
0598 {
0599     unsigned int reg;
0600 
0601     /* set up spdif, enable burst mode */
0602     reg = atiixp_read(chip, CMD);
0603     reg |= 0x02 << ATI_REG_CMD_SPDF_THRESHOLD_SHIFT;
0604     reg |= ATI_REG_CMD_BURST_EN;
0605     atiixp_write(chip, CMD, reg);
0606 
0607     reg = atiixp_read(chip, SPDF_CMD);
0608     reg &= ~(ATI_REG_SPDF_CMD_LFSR|ATI_REG_SPDF_CMD_SINGLE_CH);
0609     atiixp_write(chip, SPDF_CMD, reg);
0610 
0611     /* clear all interrupt source */
0612     atiixp_write(chip, ISR, 0xffffffff);
0613     /* enable irqs */
0614     atiixp_write(chip, IER,
0615              ATI_REG_IER_IO_STATUS_EN |
0616              ATI_REG_IER_IN_XRUN_EN |
0617              ATI_REG_IER_OUT_XRUN_EN |
0618              ATI_REG_IER_SPDF_XRUN_EN |
0619              ATI_REG_IER_SPDF_STATUS_EN);
0620     return 0;
0621 }
0622 
0623 
0624 /*
0625  * disable DMA and IRQs
0626  */
0627 static int snd_atiixp_chip_stop(struct atiixp *chip)
0628 {
0629     /* clear interrupt source */
0630     atiixp_write(chip, ISR, atiixp_read(chip, ISR));
0631     /* disable irqs */
0632     atiixp_write(chip, IER, 0);
0633     return 0;
0634 }
0635 
0636 
0637 /*
0638  * PCM section
0639  */
0640 
0641 /*
0642  * pointer callback simplly reads XXX_DMA_DT_CUR register as the current
0643  * position.  when SG-buffer is implemented, the offset must be calculated
0644  * correctly...
0645  */
0646 static snd_pcm_uframes_t snd_atiixp_pcm_pointer(struct snd_pcm_substream *substream)
0647 {
0648     struct atiixp *chip = snd_pcm_substream_chip(substream);
0649     struct snd_pcm_runtime *runtime = substream->runtime;
0650     struct atiixp_dma *dma = runtime->private_data;
0651     unsigned int curptr;
0652     int timeout = 1000;
0653 
0654     while (timeout--) {
0655         curptr = readl(chip->remap_addr + dma->ops->dt_cur);
0656         if (curptr < dma->buf_addr)
0657             continue;
0658         curptr -= dma->buf_addr;
0659         if (curptr >= dma->buf_bytes)
0660             continue;
0661         return bytes_to_frames(runtime, curptr);
0662     }
0663     dev_dbg(chip->card->dev, "invalid DMA pointer read 0x%x (buf=%x)\n",
0664            readl(chip->remap_addr + dma->ops->dt_cur), dma->buf_addr);
0665     return 0;
0666 }
0667 
0668 /*
0669  * XRUN detected, and stop the PCM substream
0670  */
0671 static void snd_atiixp_xrun_dma(struct atiixp *chip, struct atiixp_dma *dma)
0672 {
0673     if (! dma->substream || ! dma->running)
0674         return;
0675     dev_dbg(chip->card->dev, "XRUN detected (DMA %d)\n", dma->ops->type);
0676     snd_pcm_stop_xrun(dma->substream);
0677 }
0678 
0679 /*
0680  * the period ack.  update the substream.
0681  */
0682 static void snd_atiixp_update_dma(struct atiixp *chip, struct atiixp_dma *dma)
0683 {
0684     if (! dma->substream || ! dma->running)
0685         return;
0686     snd_pcm_period_elapsed(dma->substream);
0687 }
0688 
0689 /* set BUS_BUSY interrupt bit if any DMA is running */
0690 /* call with spinlock held */
0691 static void snd_atiixp_check_bus_busy(struct atiixp *chip)
0692 {
0693     unsigned int bus_busy;
0694     if (atiixp_read(chip, CMD) & (ATI_REG_CMD_SEND_EN |
0695                       ATI_REG_CMD_RECEIVE_EN |
0696                       ATI_REG_CMD_SPDF_OUT_EN))
0697         bus_busy = ATI_REG_IER_SET_BUS_BUSY;
0698     else
0699         bus_busy = 0;
0700     atiixp_update(chip, IER, ATI_REG_IER_SET_BUS_BUSY, bus_busy);
0701 }
0702 
0703 /* common trigger callback
0704  * calling the lowlevel callbacks in it
0705  */
0706 static int snd_atiixp_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
0707 {
0708     struct atiixp *chip = snd_pcm_substream_chip(substream);
0709     struct atiixp_dma *dma = substream->runtime->private_data;
0710     int err = 0;
0711 
0712     if (snd_BUG_ON(!dma->ops->enable_transfer ||
0713                !dma->ops->flush_dma))
0714         return -EINVAL;
0715 
0716     spin_lock(&chip->reg_lock);
0717     switch (cmd) {
0718     case SNDRV_PCM_TRIGGER_START:
0719     case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
0720     case SNDRV_PCM_TRIGGER_RESUME:
0721         if (dma->running && dma->suspended &&
0722             cmd == SNDRV_PCM_TRIGGER_RESUME)
0723             writel(dma->saved_curptr, chip->remap_addr +
0724                    dma->ops->dt_cur);
0725         dma->ops->enable_transfer(chip, 1);
0726         dma->running = 1;
0727         dma->suspended = 0;
0728         break;
0729     case SNDRV_PCM_TRIGGER_STOP:
0730     case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
0731     case SNDRV_PCM_TRIGGER_SUSPEND:
0732         dma->suspended = cmd == SNDRV_PCM_TRIGGER_SUSPEND;
0733         if (dma->running && dma->suspended)
0734             dma->saved_curptr = readl(chip->remap_addr +
0735                           dma->ops->dt_cur);
0736         dma->ops->enable_transfer(chip, 0);
0737         dma->running = 0;
0738         break;
0739     default:
0740         err = -EINVAL;
0741         break;
0742     }
0743     if (! err) {
0744         snd_atiixp_check_bus_busy(chip);
0745         if (cmd == SNDRV_PCM_TRIGGER_STOP) {
0746             dma->ops->flush_dma(chip);
0747             snd_atiixp_check_bus_busy(chip);
0748         }
0749     }
0750     spin_unlock(&chip->reg_lock);
0751     return err;
0752 }
0753 
0754 
0755 /*
0756  * lowlevel callbacks for each DMA type
0757  *
0758  * every callback is supposed to be called in chip->reg_lock spinlock
0759  */
0760 
0761 /* flush FIFO of analog OUT DMA */
0762 static void atiixp_out_flush_dma(struct atiixp *chip)
0763 {
0764     atiixp_write(chip, FIFO_FLUSH, ATI_REG_FIFO_OUT_FLUSH);
0765 }
0766 
0767 /* enable/disable analog OUT DMA */
0768 static void atiixp_out_enable_dma(struct atiixp *chip, int on)
0769 {
0770     unsigned int data;
0771     data = atiixp_read(chip, CMD);
0772     if (on) {
0773         if (data & ATI_REG_CMD_OUT_DMA_EN)
0774             return;
0775         atiixp_out_flush_dma(chip);
0776         data |= ATI_REG_CMD_OUT_DMA_EN;
0777     } else
0778         data &= ~ATI_REG_CMD_OUT_DMA_EN;
0779     atiixp_write(chip, CMD, data);
0780 }
0781 
0782 /* start/stop transfer over OUT DMA */
0783 static void atiixp_out_enable_transfer(struct atiixp *chip, int on)
0784 {
0785     atiixp_update(chip, CMD, ATI_REG_CMD_SEND_EN,
0786               on ? ATI_REG_CMD_SEND_EN : 0);
0787 }
0788 
0789 /* enable/disable analog IN DMA */
0790 static void atiixp_in_enable_dma(struct atiixp *chip, int on)
0791 {
0792     atiixp_update(chip, CMD, ATI_REG_CMD_IN_DMA_EN,
0793               on ? ATI_REG_CMD_IN_DMA_EN : 0);
0794 }
0795 
0796 /* start/stop analog IN DMA */
0797 static void atiixp_in_enable_transfer(struct atiixp *chip, int on)
0798 {
0799     if (on) {
0800         unsigned int data = atiixp_read(chip, CMD);
0801         if (! (data & ATI_REG_CMD_RECEIVE_EN)) {
0802             data |= ATI_REG_CMD_RECEIVE_EN;
0803 #if 0 /* FIXME: this causes the endless loop */
0804             /* wait until slot 3/4 are finished */
0805             while ((atiixp_read(chip, COUNTER) &
0806                 ATI_REG_COUNTER_SLOT) != 5)
0807                 ;
0808 #endif
0809             atiixp_write(chip, CMD, data);
0810         }
0811     } else
0812         atiixp_update(chip, CMD, ATI_REG_CMD_RECEIVE_EN, 0);
0813 }
0814 
0815 /* flush FIFO of analog IN DMA */
0816 static void atiixp_in_flush_dma(struct atiixp *chip)
0817 {
0818     atiixp_write(chip, FIFO_FLUSH, ATI_REG_FIFO_IN_FLUSH);
0819 }
0820 
0821 /* enable/disable SPDIF OUT DMA */
0822 static void atiixp_spdif_enable_dma(struct atiixp *chip, int on)
0823 {
0824     atiixp_update(chip, CMD, ATI_REG_CMD_SPDF_DMA_EN,
0825               on ? ATI_REG_CMD_SPDF_DMA_EN : 0);
0826 }
0827 
0828 /* start/stop SPDIF OUT DMA */
0829 static void atiixp_spdif_enable_transfer(struct atiixp *chip, int on)
0830 {
0831     unsigned int data;
0832     data = atiixp_read(chip, CMD);
0833     if (on)
0834         data |= ATI_REG_CMD_SPDF_OUT_EN;
0835     else
0836         data &= ~ATI_REG_CMD_SPDF_OUT_EN;
0837     atiixp_write(chip, CMD, data);
0838 }
0839 
0840 /* flush FIFO of SPDIF OUT DMA */
0841 static void atiixp_spdif_flush_dma(struct atiixp *chip)
0842 {
0843     int timeout;
0844 
0845     /* DMA off, transfer on */
0846     atiixp_spdif_enable_dma(chip, 0);
0847     atiixp_spdif_enable_transfer(chip, 1);
0848     
0849     timeout = 100;
0850     do {
0851         if (! (atiixp_read(chip, SPDF_DMA_DT_SIZE) & ATI_REG_DMA_FIFO_USED))
0852             break;
0853         udelay(1);
0854     } while (timeout-- > 0);
0855 
0856     atiixp_spdif_enable_transfer(chip, 0);
0857 }
0858 
0859 /* set up slots and formats for SPDIF OUT */
0860 static int snd_atiixp_spdif_prepare(struct snd_pcm_substream *substream)
0861 {
0862     struct atiixp *chip = snd_pcm_substream_chip(substream);
0863 
0864     spin_lock_irq(&chip->reg_lock);
0865     if (chip->spdif_over_aclink) {
0866         unsigned int data;
0867         /* enable slots 10/11 */
0868         atiixp_update(chip, CMD, ATI_REG_CMD_SPDF_CONFIG_MASK,
0869                   ATI_REG_CMD_SPDF_CONFIG_01);
0870         data = atiixp_read(chip, OUT_DMA_SLOT) & ~ATI_REG_OUT_DMA_SLOT_MASK;
0871         data |= ATI_REG_OUT_DMA_SLOT_BIT(10) |
0872             ATI_REG_OUT_DMA_SLOT_BIT(11);
0873         data |= 0x04 << ATI_REG_OUT_DMA_THRESHOLD_SHIFT;
0874         atiixp_write(chip, OUT_DMA_SLOT, data);
0875         atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_OUT,
0876                   substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE ?
0877                   ATI_REG_CMD_INTERLEAVE_OUT : 0);
0878     } else {
0879         atiixp_update(chip, CMD, ATI_REG_CMD_SPDF_CONFIG_MASK, 0);
0880         atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_SPDF, 0);
0881     }
0882     spin_unlock_irq(&chip->reg_lock);
0883     return 0;
0884 }
0885 
0886 /* set up slots and formats for analog OUT */
0887 static int snd_atiixp_playback_prepare(struct snd_pcm_substream *substream)
0888 {
0889     struct atiixp *chip = snd_pcm_substream_chip(substream);
0890     unsigned int data;
0891 
0892     spin_lock_irq(&chip->reg_lock);
0893     data = atiixp_read(chip, OUT_DMA_SLOT) & ~ATI_REG_OUT_DMA_SLOT_MASK;
0894     switch (substream->runtime->channels) {
0895     case 8:
0896         data |= ATI_REG_OUT_DMA_SLOT_BIT(10) |
0897             ATI_REG_OUT_DMA_SLOT_BIT(11);
0898         fallthrough;
0899     case 6:
0900         data |= ATI_REG_OUT_DMA_SLOT_BIT(7) |
0901             ATI_REG_OUT_DMA_SLOT_BIT(8);
0902         fallthrough;
0903     case 4:
0904         data |= ATI_REG_OUT_DMA_SLOT_BIT(6) |
0905             ATI_REG_OUT_DMA_SLOT_BIT(9);
0906         fallthrough;
0907     default:
0908         data |= ATI_REG_OUT_DMA_SLOT_BIT(3) |
0909             ATI_REG_OUT_DMA_SLOT_BIT(4);
0910         break;
0911     }
0912 
0913     /* set output threshold */
0914     data |= 0x04 << ATI_REG_OUT_DMA_THRESHOLD_SHIFT;
0915     atiixp_write(chip, OUT_DMA_SLOT, data);
0916 
0917     atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_OUT,
0918               substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE ?
0919               ATI_REG_CMD_INTERLEAVE_OUT : 0);
0920 
0921     /*
0922      * enable 6 channel re-ordering bit if needed
0923      */
0924     atiixp_update(chip, 6CH_REORDER, ATI_REG_6CH_REORDER_EN,
0925               substream->runtime->channels >= 6 ? ATI_REG_6CH_REORDER_EN: 0);
0926     
0927     spin_unlock_irq(&chip->reg_lock);
0928     return 0;
0929 }
0930 
0931 /* set up slots and formats for analog IN */
0932 static int snd_atiixp_capture_prepare(struct snd_pcm_substream *substream)
0933 {
0934     struct atiixp *chip = snd_pcm_substream_chip(substream);
0935 
0936     spin_lock_irq(&chip->reg_lock);
0937     atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_IN,
0938               substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE ?
0939               ATI_REG_CMD_INTERLEAVE_IN : 0);
0940     spin_unlock_irq(&chip->reg_lock);
0941     return 0;
0942 }
0943 
0944 /*
0945  * hw_params - allocate the buffer and set up buffer descriptors
0946  */
0947 static int snd_atiixp_pcm_hw_params(struct snd_pcm_substream *substream,
0948                     struct snd_pcm_hw_params *hw_params)
0949 {
0950     struct atiixp *chip = snd_pcm_substream_chip(substream);
0951     struct atiixp_dma *dma = substream->runtime->private_data;
0952     int err;
0953 
0954     dma->buf_addr = substream->runtime->dma_addr;
0955     dma->buf_bytes = params_buffer_bytes(hw_params);
0956 
0957     err = atiixp_build_dma_packets(chip, dma, substream,
0958                        params_periods(hw_params),
0959                        params_period_bytes(hw_params));
0960     if (err < 0)
0961         return err;
0962 
0963     if (dma->ac97_pcm_type >= 0) {
0964         struct ac97_pcm *pcm = chip->pcms[dma->ac97_pcm_type];
0965         /* PCM is bound to AC97 codec(s)
0966          * set up the AC97 codecs
0967          */
0968         if (dma->pcm_open_flag) {
0969             snd_ac97_pcm_close(pcm);
0970             dma->pcm_open_flag = 0;
0971         }
0972         err = snd_ac97_pcm_open(pcm, params_rate(hw_params),
0973                     params_channels(hw_params),
0974                     pcm->r[0].slots);
0975         if (err >= 0)
0976             dma->pcm_open_flag = 1;
0977     }
0978 
0979     return err;
0980 }
0981 
0982 static int snd_atiixp_pcm_hw_free(struct snd_pcm_substream *substream)
0983 {
0984     struct atiixp *chip = snd_pcm_substream_chip(substream);
0985     struct atiixp_dma *dma = substream->runtime->private_data;
0986 
0987     if (dma->pcm_open_flag) {
0988         struct ac97_pcm *pcm = chip->pcms[dma->ac97_pcm_type];
0989         snd_ac97_pcm_close(pcm);
0990         dma->pcm_open_flag = 0;
0991     }
0992     atiixp_clear_dma_packets(chip, dma, substream);
0993     return 0;
0994 }
0995 
0996 
0997 /*
0998  * pcm hardware definition, identical for all DMA types
0999  */
1000 static const struct snd_pcm_hardware snd_atiixp_pcm_hw =
1001 {
1002     .info =         (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1003                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1004                  SNDRV_PCM_INFO_PAUSE |
1005                  SNDRV_PCM_INFO_RESUME |
1006                  SNDRV_PCM_INFO_MMAP_VALID),
1007     .formats =      SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
1008     .rates =        SNDRV_PCM_RATE_48000,
1009     .rate_min =     48000,
1010     .rate_max =     48000,
1011     .channels_min =     2,
1012     .channels_max =     2,
1013     .buffer_bytes_max = 256 * 1024,
1014     .period_bytes_min = 32,
1015     .period_bytes_max = 128 * 1024,
1016     .periods_min =      2,
1017     .periods_max =      ATI_MAX_DESCRIPTORS,
1018 };
1019 
1020 static int snd_atiixp_pcm_open(struct snd_pcm_substream *substream,
1021                    struct atiixp_dma *dma, int pcm_type)
1022 {
1023     struct atiixp *chip = snd_pcm_substream_chip(substream);
1024     struct snd_pcm_runtime *runtime = substream->runtime;
1025     int err;
1026 
1027     if (snd_BUG_ON(!dma->ops || !dma->ops->enable_dma))
1028         return -EINVAL;
1029 
1030     if (dma->opened)
1031         return -EBUSY;
1032     dma->substream = substream;
1033     runtime->hw = snd_atiixp_pcm_hw;
1034     dma->ac97_pcm_type = pcm_type;
1035     if (pcm_type >= 0) {
1036         runtime->hw.rates = chip->pcms[pcm_type]->rates;
1037         snd_pcm_limit_hw_rates(runtime);
1038     } else {
1039         /* direct SPDIF */
1040         runtime->hw.formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE;
1041     }
1042     err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1043     if (err < 0)
1044         return err;
1045     runtime->private_data = dma;
1046 
1047     /* enable DMA bits */
1048     spin_lock_irq(&chip->reg_lock);
1049     dma->ops->enable_dma(chip, 1);
1050     spin_unlock_irq(&chip->reg_lock);
1051     dma->opened = 1;
1052 
1053     return 0;
1054 }
1055 
1056 static int snd_atiixp_pcm_close(struct snd_pcm_substream *substream,
1057                 struct atiixp_dma *dma)
1058 {
1059     struct atiixp *chip = snd_pcm_substream_chip(substream);
1060     /* disable DMA bits */
1061     if (snd_BUG_ON(!dma->ops || !dma->ops->enable_dma))
1062         return -EINVAL;
1063     spin_lock_irq(&chip->reg_lock);
1064     dma->ops->enable_dma(chip, 0);
1065     spin_unlock_irq(&chip->reg_lock);
1066     dma->substream = NULL;
1067     dma->opened = 0;
1068     return 0;
1069 }
1070 
1071 /*
1072  */
1073 static int snd_atiixp_playback_open(struct snd_pcm_substream *substream)
1074 {
1075     struct atiixp *chip = snd_pcm_substream_chip(substream);
1076     int err;
1077 
1078     mutex_lock(&chip->open_mutex);
1079     err = snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_PLAYBACK], 0);
1080     mutex_unlock(&chip->open_mutex);
1081     if (err < 0)
1082         return err;
1083     substream->runtime->hw.channels_max = chip->max_channels;
1084     if (chip->max_channels > 2)
1085         /* channels must be even */
1086         snd_pcm_hw_constraint_step(substream->runtime, 0,
1087                        SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1088     return 0;
1089 }
1090 
1091 static int snd_atiixp_playback_close(struct snd_pcm_substream *substream)
1092 {
1093     struct atiixp *chip = snd_pcm_substream_chip(substream);
1094     int err;
1095     mutex_lock(&chip->open_mutex);
1096     err = snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_PLAYBACK]);
1097     mutex_unlock(&chip->open_mutex);
1098     return err;
1099 }
1100 
1101 static int snd_atiixp_capture_open(struct snd_pcm_substream *substream)
1102 {
1103     struct atiixp *chip = snd_pcm_substream_chip(substream);
1104     return snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_CAPTURE], 1);
1105 }
1106 
1107 static int snd_atiixp_capture_close(struct snd_pcm_substream *substream)
1108 {
1109     struct atiixp *chip = snd_pcm_substream_chip(substream);
1110     return snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_CAPTURE]);
1111 }
1112 
1113 static int snd_atiixp_spdif_open(struct snd_pcm_substream *substream)
1114 {
1115     struct atiixp *chip = snd_pcm_substream_chip(substream);
1116     int err;
1117     mutex_lock(&chip->open_mutex);
1118     if (chip->spdif_over_aclink) /* share DMA_PLAYBACK */
1119         err = snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_PLAYBACK], 2);
1120     else
1121         err = snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_SPDIF], -1);
1122     mutex_unlock(&chip->open_mutex);
1123     return err;
1124 }
1125 
1126 static int snd_atiixp_spdif_close(struct snd_pcm_substream *substream)
1127 {
1128     struct atiixp *chip = snd_pcm_substream_chip(substream);
1129     int err;
1130     mutex_lock(&chip->open_mutex);
1131     if (chip->spdif_over_aclink)
1132         err = snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_PLAYBACK]);
1133     else
1134         err = snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_SPDIF]);
1135     mutex_unlock(&chip->open_mutex);
1136     return err;
1137 }
1138 
1139 /* AC97 playback */
1140 static const struct snd_pcm_ops snd_atiixp_playback_ops = {
1141     .open =     snd_atiixp_playback_open,
1142     .close =    snd_atiixp_playback_close,
1143     .hw_params =    snd_atiixp_pcm_hw_params,
1144     .hw_free =  snd_atiixp_pcm_hw_free,
1145     .prepare =  snd_atiixp_playback_prepare,
1146     .trigger =  snd_atiixp_pcm_trigger,
1147     .pointer =  snd_atiixp_pcm_pointer,
1148 };
1149 
1150 /* AC97 capture */
1151 static const struct snd_pcm_ops snd_atiixp_capture_ops = {
1152     .open =     snd_atiixp_capture_open,
1153     .close =    snd_atiixp_capture_close,
1154     .hw_params =    snd_atiixp_pcm_hw_params,
1155     .hw_free =  snd_atiixp_pcm_hw_free,
1156     .prepare =  snd_atiixp_capture_prepare,
1157     .trigger =  snd_atiixp_pcm_trigger,
1158     .pointer =  snd_atiixp_pcm_pointer,
1159 };
1160 
1161 /* SPDIF playback */
1162 static const struct snd_pcm_ops snd_atiixp_spdif_ops = {
1163     .open =     snd_atiixp_spdif_open,
1164     .close =    snd_atiixp_spdif_close,
1165     .hw_params =    snd_atiixp_pcm_hw_params,
1166     .hw_free =  snd_atiixp_pcm_hw_free,
1167     .prepare =  snd_atiixp_spdif_prepare,
1168     .trigger =  snd_atiixp_pcm_trigger,
1169     .pointer =  snd_atiixp_pcm_pointer,
1170 };
1171 
1172 static const struct ac97_pcm atiixp_pcm_defs[] = {
1173     /* front PCM */
1174     {
1175         .exclusive = 1,
1176         .r = {  {
1177                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1178                      (1 << AC97_SLOT_PCM_RIGHT) |
1179                      (1 << AC97_SLOT_PCM_CENTER) |
1180                      (1 << AC97_SLOT_PCM_SLEFT) |
1181                      (1 << AC97_SLOT_PCM_SRIGHT) |
1182                      (1 << AC97_SLOT_LFE)
1183             }
1184         }
1185     },
1186     /* PCM IN #1 */
1187     {
1188         .stream = 1,
1189         .exclusive = 1,
1190         .r = {  {
1191                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1192                      (1 << AC97_SLOT_PCM_RIGHT)
1193             }
1194         }
1195     },
1196     /* S/PDIF OUT (optional) */
1197     {
1198         .exclusive = 1,
1199         .spdif = 1,
1200         .r = {  {
1201                 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1202                      (1 << AC97_SLOT_SPDIF_RIGHT2)
1203             }
1204         }
1205     },
1206 };
1207 
1208 static const struct atiixp_dma_ops snd_atiixp_playback_dma_ops = {
1209     .type = ATI_DMA_PLAYBACK,
1210     .llp_offset = ATI_REG_OUT_DMA_LINKPTR,
1211     .dt_cur = ATI_REG_OUT_DMA_DT_CUR,
1212     .enable_dma = atiixp_out_enable_dma,
1213     .enable_transfer = atiixp_out_enable_transfer,
1214     .flush_dma = atiixp_out_flush_dma,
1215 };
1216     
1217 static const struct atiixp_dma_ops snd_atiixp_capture_dma_ops = {
1218     .type = ATI_DMA_CAPTURE,
1219     .llp_offset = ATI_REG_IN_DMA_LINKPTR,
1220     .dt_cur = ATI_REG_IN_DMA_DT_CUR,
1221     .enable_dma = atiixp_in_enable_dma,
1222     .enable_transfer = atiixp_in_enable_transfer,
1223     .flush_dma = atiixp_in_flush_dma,
1224 };
1225     
1226 static const struct atiixp_dma_ops snd_atiixp_spdif_dma_ops = {
1227     .type = ATI_DMA_SPDIF,
1228     .llp_offset = ATI_REG_SPDF_DMA_LINKPTR,
1229     .dt_cur = ATI_REG_SPDF_DMA_DT_CUR,
1230     .enable_dma = atiixp_spdif_enable_dma,
1231     .enable_transfer = atiixp_spdif_enable_transfer,
1232     .flush_dma = atiixp_spdif_flush_dma,
1233 };
1234     
1235 
1236 static int snd_atiixp_pcm_new(struct atiixp *chip)
1237 {
1238     struct snd_pcm *pcm;
1239     struct snd_pcm_chmap *chmap;
1240     struct snd_ac97_bus *pbus = chip->ac97_bus;
1241     int err, i, num_pcms;
1242 
1243     /* initialize constants */
1244     chip->dmas[ATI_DMA_PLAYBACK].ops = &snd_atiixp_playback_dma_ops;
1245     chip->dmas[ATI_DMA_CAPTURE].ops = &snd_atiixp_capture_dma_ops;
1246     if (! chip->spdif_over_aclink)
1247         chip->dmas[ATI_DMA_SPDIF].ops = &snd_atiixp_spdif_dma_ops;
1248 
1249     /* assign AC97 pcm */
1250     if (chip->spdif_over_aclink)
1251         num_pcms = 3;
1252     else
1253         num_pcms = 2;
1254     err = snd_ac97_pcm_assign(pbus, num_pcms, atiixp_pcm_defs);
1255     if (err < 0)
1256         return err;
1257     for (i = 0; i < num_pcms; i++)
1258         chip->pcms[i] = &pbus->pcms[i];
1259 
1260     chip->max_channels = 2;
1261     if (pbus->pcms[ATI_PCM_OUT].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
1262         if (pbus->pcms[ATI_PCM_OUT].r[0].slots & (1 << AC97_SLOT_LFE))
1263             chip->max_channels = 6;
1264         else
1265             chip->max_channels = 4;
1266     }
1267 
1268     /* PCM #0: analog I/O */
1269     err = snd_pcm_new(chip->card, "ATI IXP AC97",
1270               ATI_PCMDEV_ANALOG, 1, 1, &pcm);
1271     if (err < 0)
1272         return err;
1273     snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_atiixp_playback_ops);
1274     snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_atiixp_capture_ops);
1275     pcm->private_data = chip;
1276     strcpy(pcm->name, "ATI IXP AC97");
1277     chip->pcmdevs[ATI_PCMDEV_ANALOG] = pcm;
1278 
1279     snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1280                        &chip->pci->dev, 64*1024, 128*1024);
1281 
1282     err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1283                      snd_pcm_alt_chmaps, chip->max_channels, 0,
1284                      &chmap);
1285     if (err < 0)
1286         return err;
1287     chmap->channel_mask = SND_PCM_CHMAP_MASK_2468;
1288     chip->ac97[0]->chmaps[SNDRV_PCM_STREAM_PLAYBACK] = chmap;
1289 
1290     /* no SPDIF support on codec? */
1291     if (chip->pcms[ATI_PCM_SPDIF] && ! chip->pcms[ATI_PCM_SPDIF]->rates)
1292         return 0;
1293         
1294     /* FIXME: non-48k sample rate doesn't work on my test machine with AD1888 */
1295     if (chip->pcms[ATI_PCM_SPDIF])
1296         chip->pcms[ATI_PCM_SPDIF]->rates = SNDRV_PCM_RATE_48000;
1297 
1298     /* PCM #1: spdif playback */
1299     err = snd_pcm_new(chip->card, "ATI IXP IEC958",
1300               ATI_PCMDEV_DIGITAL, 1, 0, &pcm);
1301     if (err < 0)
1302         return err;
1303     snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_atiixp_spdif_ops);
1304     pcm->private_data = chip;
1305     if (chip->spdif_over_aclink)
1306         strcpy(pcm->name, "ATI IXP IEC958 (AC97)");
1307     else
1308         strcpy(pcm->name, "ATI IXP IEC958 (Direct)");
1309     chip->pcmdevs[ATI_PCMDEV_DIGITAL] = pcm;
1310 
1311     snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1312                        &chip->pci->dev, 64*1024, 128*1024);
1313 
1314     /* pre-select AC97 SPDIF slots 10/11 */
1315     for (i = 0; i < NUM_ATI_CODECS; i++) {
1316         if (chip->ac97[i])
1317             snd_ac97_update_bits(chip->ac97[i],
1318                          AC97_EXTENDED_STATUS,
1319                          0x03 << 4, 0x03 << 4);
1320     }
1321 
1322     return 0;
1323 }
1324 
1325 
1326 
1327 /*
1328  * interrupt handler
1329  */
1330 static irqreturn_t snd_atiixp_interrupt(int irq, void *dev_id)
1331 {
1332     struct atiixp *chip = dev_id;
1333     unsigned int status;
1334 
1335     status = atiixp_read(chip, ISR);
1336 
1337     if (! status)
1338         return IRQ_NONE;
1339 
1340     /* process audio DMA */
1341     if (status & ATI_REG_ISR_OUT_XRUN)
1342         snd_atiixp_xrun_dma(chip,  &chip->dmas[ATI_DMA_PLAYBACK]);
1343     else if (status & ATI_REG_ISR_OUT_STATUS)
1344         snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_PLAYBACK]);
1345     if (status & ATI_REG_ISR_IN_XRUN)
1346         snd_atiixp_xrun_dma(chip,  &chip->dmas[ATI_DMA_CAPTURE]);
1347     else if (status & ATI_REG_ISR_IN_STATUS)
1348         snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_CAPTURE]);
1349     if (! chip->spdif_over_aclink) {
1350         if (status & ATI_REG_ISR_SPDF_XRUN)
1351             snd_atiixp_xrun_dma(chip,  &chip->dmas[ATI_DMA_SPDIF]);
1352         else if (status & ATI_REG_ISR_SPDF_STATUS)
1353             snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_SPDIF]);
1354     }
1355 
1356     /* for codec detection */
1357     if (status & CODEC_CHECK_BITS) {
1358         unsigned int detected;
1359         detected = status & CODEC_CHECK_BITS;
1360         spin_lock(&chip->reg_lock);
1361         chip->codec_not_ready_bits |= detected;
1362         atiixp_update(chip, IER, detected, 0); /* disable the detected irqs */
1363         spin_unlock(&chip->reg_lock);
1364     }
1365 
1366     /* ack */
1367     atiixp_write(chip, ISR, status);
1368 
1369     return IRQ_HANDLED;
1370 }
1371 
1372 
1373 /*
1374  * ac97 mixer section
1375  */
1376 
1377 static const struct ac97_quirk ac97_quirks[] = {
1378     {
1379         .subvendor = 0x103c,
1380         .subdevice = 0x006b,
1381         .name = "HP Pavilion ZV5030US",
1382         .type = AC97_TUNE_MUTE_LED
1383     },
1384     {
1385         .subvendor = 0x103c,
1386         .subdevice = 0x308b,
1387         .name = "HP nx6125",
1388         .type = AC97_TUNE_MUTE_LED
1389     },
1390     {
1391         .subvendor = 0x103c,
1392         .subdevice = 0x3091,
1393         .name = "unknown HP",
1394         .type = AC97_TUNE_MUTE_LED
1395     },
1396     { } /* terminator */
1397 };
1398 
1399 static int snd_atiixp_mixer_new(struct atiixp *chip, int clock,
1400                 const char *quirk_override)
1401 {
1402     struct snd_ac97_bus *pbus;
1403     struct snd_ac97_template ac97;
1404     int i, err;
1405     int codec_count;
1406     static const struct snd_ac97_bus_ops ops = {
1407         .write = snd_atiixp_ac97_write,
1408         .read = snd_atiixp_ac97_read,
1409     };
1410     static const unsigned int codec_skip[NUM_ATI_CODECS] = {
1411         ATI_REG_ISR_CODEC0_NOT_READY,
1412         ATI_REG_ISR_CODEC1_NOT_READY,
1413         ATI_REG_ISR_CODEC2_NOT_READY,
1414     };
1415 
1416     if (snd_atiixp_codec_detect(chip) < 0)
1417         return -ENXIO;
1418 
1419     err = snd_ac97_bus(chip->card, 0, &ops, chip, &pbus);
1420     if (err < 0)
1421         return err;
1422     pbus->clock = clock;
1423     chip->ac97_bus = pbus;
1424 
1425     codec_count = 0;
1426     for (i = 0; i < NUM_ATI_CODECS; i++) {
1427         if (chip->codec_not_ready_bits & codec_skip[i])
1428             continue;
1429         memset(&ac97, 0, sizeof(ac97));
1430         ac97.private_data = chip;
1431         ac97.pci = chip->pci;
1432         ac97.num = i;
1433         ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE;
1434         if (! chip->spdif_over_aclink)
1435             ac97.scaps |= AC97_SCAP_NO_SPDIF;
1436         err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i]);
1437         if (err < 0) {
1438             chip->ac97[i] = NULL; /* to be sure */
1439             dev_dbg(chip->card->dev,
1440                 "codec %d not available for audio\n", i);
1441             continue;
1442         }
1443         codec_count++;
1444     }
1445 
1446     if (! codec_count) {
1447         dev_err(chip->card->dev, "no codec available\n");
1448         return -ENODEV;
1449     }
1450 
1451     snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
1452 
1453     return 0;
1454 }
1455 
1456 
1457 #ifdef CONFIG_PM_SLEEP
1458 /*
1459  * power management
1460  */
1461 static int snd_atiixp_suspend(struct device *dev)
1462 {
1463     struct snd_card *card = dev_get_drvdata(dev);
1464     struct atiixp *chip = card->private_data;
1465     int i;
1466 
1467     snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1468     for (i = 0; i < NUM_ATI_CODECS; i++)
1469         snd_ac97_suspend(chip->ac97[i]);
1470     snd_atiixp_aclink_down(chip);
1471     snd_atiixp_chip_stop(chip);
1472     return 0;
1473 }
1474 
1475 static int snd_atiixp_resume(struct device *dev)
1476 {
1477     struct snd_card *card = dev_get_drvdata(dev);
1478     struct atiixp *chip = card->private_data;
1479     int i;
1480 
1481     snd_atiixp_aclink_reset(chip);
1482     snd_atiixp_chip_start(chip);
1483 
1484     for (i = 0; i < NUM_ATI_CODECS; i++)
1485         snd_ac97_resume(chip->ac97[i]);
1486 
1487     for (i = 0; i < NUM_ATI_PCMDEVS; i++)
1488         if (chip->pcmdevs[i]) {
1489             struct atiixp_dma *dma = &chip->dmas[i];
1490             if (dma->substream && dma->suspended) {
1491                 dma->ops->enable_dma(chip, 1);
1492                 dma->substream->ops->prepare(dma->substream);
1493                 writel((u32)dma->desc_buf.addr | ATI_REG_LINKPTR_EN,
1494                        chip->remap_addr + dma->ops->llp_offset);
1495             }
1496         }
1497 
1498     snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1499     return 0;
1500 }
1501 
1502 static SIMPLE_DEV_PM_OPS(snd_atiixp_pm, snd_atiixp_suspend, snd_atiixp_resume);
1503 #define SND_ATIIXP_PM_OPS   &snd_atiixp_pm
1504 #else
1505 #define SND_ATIIXP_PM_OPS   NULL
1506 #endif /* CONFIG_PM_SLEEP */
1507 
1508 
1509 /*
1510  * proc interface for register dump
1511  */
1512 
1513 static void snd_atiixp_proc_read(struct snd_info_entry *entry,
1514                  struct snd_info_buffer *buffer)
1515 {
1516     struct atiixp *chip = entry->private_data;
1517     int i;
1518 
1519     for (i = 0; i < 256; i += 4)
1520         snd_iprintf(buffer, "%02x: %08x\n", i, readl(chip->remap_addr + i));
1521 }
1522 
1523 static void snd_atiixp_proc_init(struct atiixp *chip)
1524 {
1525     snd_card_ro_proc_new(chip->card, "atiixp", chip, snd_atiixp_proc_read);
1526 }
1527 
1528 
1529 /*
1530  * destructor
1531  */
1532 
1533 static void snd_atiixp_free(struct snd_card *card)
1534 {
1535     snd_atiixp_chip_stop(card->private_data);
1536 }
1537 
1538 /*
1539  * constructor for chip instance
1540  */
1541 static int snd_atiixp_init(struct snd_card *card, struct pci_dev *pci)
1542 {
1543     struct atiixp *chip = card->private_data;
1544     int err;
1545 
1546     err = pcim_enable_device(pci);
1547     if (err < 0)
1548         return err;
1549 
1550     spin_lock_init(&chip->reg_lock);
1551     mutex_init(&chip->open_mutex);
1552     chip->card = card;
1553     chip->pci = pci;
1554     chip->irq = -1;
1555     err = pcim_iomap_regions(pci, 1 << 0, "ATI IXP AC97");
1556     if (err < 0)
1557         return err;
1558     chip->addr = pci_resource_start(pci, 0);
1559     chip->remap_addr = pcim_iomap_table(pci)[0];
1560 
1561     if (devm_request_irq(&pci->dev, pci->irq, snd_atiixp_interrupt,
1562                  IRQF_SHARED, KBUILD_MODNAME, chip)) {
1563         dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
1564         return -EBUSY;
1565     }
1566     chip->irq = pci->irq;
1567     card->sync_irq = chip->irq;
1568     card->private_free = snd_atiixp_free;
1569     pci_set_master(pci);
1570 
1571     return 0;
1572 }
1573 
1574 
1575 static int __snd_atiixp_probe(struct pci_dev *pci,
1576                   const struct pci_device_id *pci_id)
1577 {
1578     struct snd_card *card;
1579     struct atiixp *chip;
1580     int err;
1581 
1582     err = snd_devm_card_new(&pci->dev, index, id, THIS_MODULE,
1583                 sizeof(*chip), &card);
1584     if (err < 0)
1585         return err;
1586     chip = card->private_data;
1587 
1588     strcpy(card->driver, spdif_aclink ? "ATIIXP" : "ATIIXP-SPDMA");
1589     strcpy(card->shortname, "ATI IXP");
1590     err = snd_atiixp_init(card, pci);
1591     if (err < 0)
1592         return err;
1593 
1594     err = snd_atiixp_aclink_reset(chip);
1595     if (err < 0)
1596         return err;
1597 
1598     chip->spdif_over_aclink = spdif_aclink;
1599 
1600     err = snd_atiixp_mixer_new(chip, ac97_clock, ac97_quirk);
1601     if (err < 0)
1602         return err;
1603 
1604     err = snd_atiixp_pcm_new(chip);
1605     if (err < 0)
1606         return err;
1607     
1608     snd_atiixp_proc_init(chip);
1609 
1610     snd_atiixp_chip_start(chip);
1611 
1612     snprintf(card->longname, sizeof(card->longname),
1613          "%s rev %x with %s at %#lx, irq %i", card->shortname,
1614          pci->revision,
1615          chip->ac97[0] ? snd_ac97_get_short_name(chip->ac97[0]) : "?",
1616          chip->addr, chip->irq);
1617 
1618     err = snd_card_register(card);
1619     if (err < 0)
1620         return err;
1621 
1622     pci_set_drvdata(pci, card);
1623     return 0;
1624 }
1625 
1626 static int snd_atiixp_probe(struct pci_dev *pci,
1627                 const struct pci_device_id *pci_id)
1628 {
1629     return snd_card_free_on_error(&pci->dev, __snd_atiixp_probe(pci, pci_id));
1630 }
1631 
1632 static struct pci_driver atiixp_driver = {
1633     .name = KBUILD_MODNAME,
1634     .id_table = snd_atiixp_ids,
1635     .probe = snd_atiixp_probe,
1636     .driver = {
1637         .pm = SND_ATIIXP_PM_OPS,
1638     },
1639 };
1640 
1641 module_pci_driver(atiixp_driver);
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