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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /* Analog Devices 1889 audio driver
0003  *
0004  * This is a driver for the AD1889 PCI audio chipset found
0005  * on the HP PA-RISC [BCJ]-xxx0 workstations.
0006  *
0007  * Copyright (C) 2004-2005, Kyle McMartin <kyle@parisc-linux.org>
0008  * Copyright (C) 2005, Thibaut Varene <varenet@parisc-linux.org>
0009  *   Based on the OSS AD1889 driver by Randolph Chung <tausq@debian.org>
0010  *
0011  * TODO:
0012  *  Do we need to take care of CCS register?
0013  *  Maybe we could use finer grained locking (separate locks for pb/cap)?
0014  * Wishlist:
0015  *  Control Interface (mixer) support
0016  *  Better AC97 support (VSR...)?
0017  *  PM support
0018  *  MIDI support
0019  *  Game Port support
0020  *  SG DMA support (this will need *a lot* of work)
0021  */
0022 
0023 #include <linux/init.h>
0024 #include <linux/pci.h>
0025 #include <linux/dma-mapping.h>
0026 #include <linux/slab.h>
0027 #include <linux/interrupt.h>
0028 #include <linux/compiler.h>
0029 #include <linux/delay.h>
0030 #include <linux/module.h>
0031 #include <linux/io.h>
0032 
0033 #include <sound/core.h>
0034 #include <sound/pcm.h>
0035 #include <sound/initval.h>
0036 #include <sound/ac97_codec.h>
0037 
0038 #include "ad1889.h"
0039 #include "ac97/ac97_id.h"
0040 
0041 #define AD1889_DRVVER   "Version: 1.7"
0042 
0043 MODULE_AUTHOR("Kyle McMartin <kyle@parisc-linux.org>, Thibaut Varene <t-bone@parisc-linux.org>");
0044 MODULE_DESCRIPTION("Analog Devices AD1889 ALSA sound driver");
0045 MODULE_LICENSE("GPL");
0046 
0047 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
0048 module_param_array(index, int, NULL, 0444);
0049 MODULE_PARM_DESC(index, "Index value for the AD1889 soundcard.");
0050 
0051 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
0052 module_param_array(id, charp, NULL, 0444);
0053 MODULE_PARM_DESC(id, "ID string for the AD1889 soundcard.");
0054 
0055 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
0056 module_param_array(enable, bool, NULL, 0444);
0057 MODULE_PARM_DESC(enable, "Enable AD1889 soundcard.");
0058 
0059 static char *ac97_quirk[SNDRV_CARDS];
0060 module_param_array(ac97_quirk, charp, NULL, 0444);
0061 MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
0062 
0063 #define DEVNAME "ad1889"
0064 #define PFX DEVNAME ": "
0065 
0066 /* keep track of some hw registers */
0067 struct ad1889_register_state {
0068     u16 reg;    /* reg setup */
0069     u32 addr;   /* dma base address */
0070     unsigned long size; /* DMA buffer size */
0071 };
0072 
0073 struct snd_ad1889 {
0074     struct snd_card *card;
0075     struct pci_dev *pci;
0076 
0077     int irq;
0078     unsigned long bar;
0079     void __iomem *iobase;
0080 
0081     struct snd_ac97 *ac97;
0082     struct snd_ac97_bus *ac97_bus;
0083     struct snd_pcm *pcm;
0084     struct snd_info_entry *proc;
0085 
0086     struct snd_pcm_substream *psubs;
0087     struct snd_pcm_substream *csubs;
0088 
0089     /* playback register state */
0090     struct ad1889_register_state wave;
0091     struct ad1889_register_state ramc;
0092 
0093     spinlock_t lock;
0094 };
0095 
0096 static inline u16
0097 ad1889_readw(struct snd_ad1889 *chip, unsigned reg)
0098 {
0099     return readw(chip->iobase + reg);
0100 }
0101 
0102 static inline void
0103 ad1889_writew(struct snd_ad1889 *chip, unsigned reg, u16 val)
0104 {
0105     writew(val, chip->iobase + reg);
0106 }
0107 
0108 static inline u32
0109 ad1889_readl(struct snd_ad1889 *chip, unsigned reg)
0110 {
0111     return readl(chip->iobase + reg);
0112 }
0113 
0114 static inline void
0115 ad1889_writel(struct snd_ad1889 *chip, unsigned reg, u32 val)
0116 {
0117     writel(val, chip->iobase + reg);
0118 }
0119 
0120 static inline void
0121 ad1889_unmute(struct snd_ad1889 *chip)
0122 {
0123     u16 st;
0124     st = ad1889_readw(chip, AD_DS_WADA) & 
0125         ~(AD_DS_WADA_RWAM | AD_DS_WADA_LWAM);
0126     ad1889_writew(chip, AD_DS_WADA, st);
0127     ad1889_readw(chip, AD_DS_WADA);
0128 }
0129 
0130 static inline void
0131 ad1889_mute(struct snd_ad1889 *chip)
0132 {
0133     u16 st;
0134     st = ad1889_readw(chip, AD_DS_WADA) | AD_DS_WADA_RWAM | AD_DS_WADA_LWAM;
0135     ad1889_writew(chip, AD_DS_WADA, st);
0136     ad1889_readw(chip, AD_DS_WADA);
0137 }
0138 
0139 static inline void
0140 ad1889_load_adc_buffer_address(struct snd_ad1889 *chip, u32 address)
0141 {
0142     ad1889_writel(chip, AD_DMA_ADCBA, address);
0143     ad1889_writel(chip, AD_DMA_ADCCA, address);
0144 }
0145 
0146 static inline void
0147 ad1889_load_adc_buffer_count(struct snd_ad1889 *chip, u32 count)
0148 {
0149     ad1889_writel(chip, AD_DMA_ADCBC, count);
0150     ad1889_writel(chip, AD_DMA_ADCCC, count);
0151 }
0152 
0153 static inline void
0154 ad1889_load_adc_interrupt_count(struct snd_ad1889 *chip, u32 count)
0155 {
0156     ad1889_writel(chip, AD_DMA_ADCIB, count);
0157     ad1889_writel(chip, AD_DMA_ADCIC, count);
0158 }
0159 
0160 static inline void
0161 ad1889_load_wave_buffer_address(struct snd_ad1889 *chip, u32 address)
0162 {
0163     ad1889_writel(chip, AD_DMA_WAVBA, address);
0164     ad1889_writel(chip, AD_DMA_WAVCA, address);
0165 }
0166 
0167 static inline void
0168 ad1889_load_wave_buffer_count(struct snd_ad1889 *chip, u32 count)
0169 {
0170     ad1889_writel(chip, AD_DMA_WAVBC, count);
0171     ad1889_writel(chip, AD_DMA_WAVCC, count);
0172 }
0173 
0174 static inline void
0175 ad1889_load_wave_interrupt_count(struct snd_ad1889 *chip, u32 count)
0176 {
0177     ad1889_writel(chip, AD_DMA_WAVIB, count);
0178     ad1889_writel(chip, AD_DMA_WAVIC, count);
0179 }
0180 
0181 static void
0182 ad1889_channel_reset(struct snd_ad1889 *chip, unsigned int channel)
0183 {
0184     u16 reg;
0185     
0186     if (channel & AD_CHAN_WAV) {
0187         /* Disable wave channel */
0188         reg = ad1889_readw(chip, AD_DS_WSMC) & ~AD_DS_WSMC_WAEN;
0189         ad1889_writew(chip, AD_DS_WSMC, reg);
0190         chip->wave.reg = reg;
0191         
0192         /* disable IRQs */
0193         reg = ad1889_readw(chip, AD_DMA_WAV);
0194         reg &= AD_DMA_IM_DIS;
0195         reg &= ~AD_DMA_LOOP;
0196         ad1889_writew(chip, AD_DMA_WAV, reg);
0197 
0198         /* clear IRQ and address counters and pointers */
0199         ad1889_load_wave_buffer_address(chip, 0x0);
0200         ad1889_load_wave_buffer_count(chip, 0x0);
0201         ad1889_load_wave_interrupt_count(chip, 0x0);
0202 
0203         /* flush */
0204         ad1889_readw(chip, AD_DMA_WAV);
0205     }
0206     
0207     if (channel & AD_CHAN_ADC) {
0208         /* Disable ADC channel */
0209         reg = ad1889_readw(chip, AD_DS_RAMC) & ~AD_DS_RAMC_ADEN;
0210         ad1889_writew(chip, AD_DS_RAMC, reg);
0211         chip->ramc.reg = reg;
0212 
0213         reg = ad1889_readw(chip, AD_DMA_ADC);
0214         reg &= AD_DMA_IM_DIS;
0215         reg &= ~AD_DMA_LOOP;
0216         ad1889_writew(chip, AD_DMA_ADC, reg);
0217     
0218         ad1889_load_adc_buffer_address(chip, 0x0);
0219         ad1889_load_adc_buffer_count(chip, 0x0);
0220         ad1889_load_adc_interrupt_count(chip, 0x0);
0221 
0222         /* flush */
0223         ad1889_readw(chip, AD_DMA_ADC);
0224     }
0225 }
0226 
0227 static u16
0228 snd_ad1889_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
0229 {
0230     struct snd_ad1889 *chip = ac97->private_data;
0231     return ad1889_readw(chip, AD_AC97_BASE + reg);
0232 }
0233 
0234 static void
0235 snd_ad1889_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val)
0236 {
0237     struct snd_ad1889 *chip = ac97->private_data;
0238     ad1889_writew(chip, AD_AC97_BASE + reg, val);
0239 }
0240 
0241 static int
0242 snd_ad1889_ac97_ready(struct snd_ad1889 *chip)
0243 {
0244     int retry = 400; /* average needs 352 msec */
0245     
0246     while (!(ad1889_readw(chip, AD_AC97_ACIC) & AD_AC97_ACIC_ACRDY) 
0247             && --retry)
0248         usleep_range(1000, 2000);
0249     if (!retry) {
0250         dev_err(chip->card->dev, "[%s] Link is not ready.\n",
0251             __func__);
0252         return -EIO;
0253     }
0254     dev_dbg(chip->card->dev, "[%s] ready after %d ms\n", __func__, 400 - retry);
0255 
0256     return 0;
0257 }
0258 
0259 static const struct snd_pcm_hardware snd_ad1889_playback_hw = {
0260     .info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
0261         SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BLOCK_TRANSFER,
0262     .formats = SNDRV_PCM_FMTBIT_S16_LE,
0263     .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
0264     .rate_min = 8000,   /* docs say 7000, but we're lazy */
0265     .rate_max = 48000,
0266     .channels_min = 1,
0267     .channels_max = 2,
0268     .buffer_bytes_max = BUFFER_BYTES_MAX,
0269     .period_bytes_min = PERIOD_BYTES_MIN,
0270     .period_bytes_max = PERIOD_BYTES_MAX,
0271     .periods_min = PERIODS_MIN,
0272     .periods_max = PERIODS_MAX,
0273     /*.fifo_size = 0,*/
0274 };
0275 
0276 static const struct snd_pcm_hardware snd_ad1889_capture_hw = {
0277     .info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
0278         SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BLOCK_TRANSFER,
0279     .formats = SNDRV_PCM_FMTBIT_S16_LE,
0280     .rates = SNDRV_PCM_RATE_48000,
0281     .rate_min = 48000,  /* docs say we could to VSR, but we're lazy */
0282     .rate_max = 48000,
0283     .channels_min = 1,
0284     .channels_max = 2,
0285     .buffer_bytes_max = BUFFER_BYTES_MAX,
0286     .period_bytes_min = PERIOD_BYTES_MIN,
0287     .period_bytes_max = PERIOD_BYTES_MAX,
0288     .periods_min = PERIODS_MIN,
0289     .periods_max = PERIODS_MAX,
0290     /*.fifo_size = 0,*/
0291 };
0292 
0293 static int
0294 snd_ad1889_playback_open(struct snd_pcm_substream *ss)
0295 {
0296     struct snd_ad1889 *chip = snd_pcm_substream_chip(ss);
0297     struct snd_pcm_runtime *rt = ss->runtime;
0298 
0299     chip->psubs = ss;
0300     rt->hw = snd_ad1889_playback_hw;
0301 
0302     return 0;
0303 }
0304 
0305 static int
0306 snd_ad1889_capture_open(struct snd_pcm_substream *ss)
0307 {
0308     struct snd_ad1889 *chip = snd_pcm_substream_chip(ss);
0309     struct snd_pcm_runtime *rt = ss->runtime;
0310 
0311     chip->csubs = ss;
0312     rt->hw = snd_ad1889_capture_hw;
0313 
0314     return 0;
0315 }
0316 
0317 static int
0318 snd_ad1889_playback_close(struct snd_pcm_substream *ss)
0319 {
0320     struct snd_ad1889 *chip = snd_pcm_substream_chip(ss);
0321     chip->psubs = NULL;
0322     return 0;
0323 }
0324 
0325 static int
0326 snd_ad1889_capture_close(struct snd_pcm_substream *ss)
0327 {
0328     struct snd_ad1889 *chip = snd_pcm_substream_chip(ss);
0329     chip->csubs = NULL;
0330     return 0;
0331 }
0332 
0333 static int
0334 snd_ad1889_playback_prepare(struct snd_pcm_substream *ss)
0335 {
0336     struct snd_ad1889 *chip = snd_pcm_substream_chip(ss);
0337     struct snd_pcm_runtime *rt = ss->runtime;
0338     unsigned int size = snd_pcm_lib_buffer_bytes(ss);
0339     unsigned int count = snd_pcm_lib_period_bytes(ss);
0340     u16 reg;
0341 
0342     ad1889_channel_reset(chip, AD_CHAN_WAV);
0343 
0344     reg = ad1889_readw(chip, AD_DS_WSMC);
0345     
0346     /* Mask out 16-bit / Stereo */
0347     reg &= ~(AD_DS_WSMC_WA16 | AD_DS_WSMC_WAST);
0348 
0349     if (snd_pcm_format_width(rt->format) == 16)
0350         reg |= AD_DS_WSMC_WA16;
0351 
0352     if (rt->channels > 1)
0353         reg |= AD_DS_WSMC_WAST;
0354 
0355     /* let's make sure we don't clobber ourselves */
0356     spin_lock_irq(&chip->lock);
0357     
0358     chip->wave.size = size;
0359     chip->wave.reg = reg;
0360     chip->wave.addr = rt->dma_addr;
0361 
0362     ad1889_writew(chip, AD_DS_WSMC, chip->wave.reg);
0363     
0364     /* Set sample rates on the codec */
0365     ad1889_writew(chip, AD_DS_WAS, rt->rate);
0366 
0367     /* Set up DMA */
0368     ad1889_load_wave_buffer_address(chip, chip->wave.addr);
0369     ad1889_load_wave_buffer_count(chip, size);
0370     ad1889_load_wave_interrupt_count(chip, count);
0371 
0372     /* writes flush */
0373     ad1889_readw(chip, AD_DS_WSMC);
0374     
0375     spin_unlock_irq(&chip->lock);
0376     
0377     dev_dbg(chip->card->dev,
0378         "prepare playback: addr = 0x%x, count = %u, size = %u, reg = 0x%x, rate = %u\n",
0379         chip->wave.addr, count, size, reg, rt->rate);
0380     return 0;
0381 }
0382 
0383 static int
0384 snd_ad1889_capture_prepare(struct snd_pcm_substream *ss)
0385 {
0386     struct snd_ad1889 *chip = snd_pcm_substream_chip(ss);
0387     struct snd_pcm_runtime *rt = ss->runtime;
0388     unsigned int size = snd_pcm_lib_buffer_bytes(ss);
0389     unsigned int count = snd_pcm_lib_period_bytes(ss);
0390     u16 reg;
0391 
0392     ad1889_channel_reset(chip, AD_CHAN_ADC);
0393     
0394     reg = ad1889_readw(chip, AD_DS_RAMC);
0395 
0396     /* Mask out 16-bit / Stereo */
0397     reg &= ~(AD_DS_RAMC_AD16 | AD_DS_RAMC_ADST);
0398 
0399     if (snd_pcm_format_width(rt->format) == 16)
0400         reg |= AD_DS_RAMC_AD16;
0401 
0402     if (rt->channels > 1)
0403         reg |= AD_DS_RAMC_ADST;
0404 
0405     /* let's make sure we don't clobber ourselves */
0406     spin_lock_irq(&chip->lock);
0407     
0408     chip->ramc.size = size;
0409     chip->ramc.reg = reg;
0410     chip->ramc.addr = rt->dma_addr;
0411 
0412     ad1889_writew(chip, AD_DS_RAMC, chip->ramc.reg);
0413 
0414     /* Set up DMA */
0415     ad1889_load_adc_buffer_address(chip, chip->ramc.addr);
0416     ad1889_load_adc_buffer_count(chip, size);
0417     ad1889_load_adc_interrupt_count(chip, count);
0418 
0419     /* writes flush */
0420     ad1889_readw(chip, AD_DS_RAMC);
0421     
0422     spin_unlock_irq(&chip->lock);
0423     
0424     dev_dbg(chip->card->dev,
0425         "prepare capture: addr = 0x%x, count = %u, size = %u, reg = 0x%x, rate = %u\n",
0426         chip->ramc.addr, count, size, reg, rt->rate);
0427     return 0;
0428 }
0429 
0430 /* this is called in atomic context with IRQ disabled.
0431    Must be as fast as possible and not sleep.
0432    DMA should be *triggered* by this call.
0433    The WSMC "WAEN" bit triggers DMA Wave On/Off */
0434 static int
0435 snd_ad1889_playback_trigger(struct snd_pcm_substream *ss, int cmd)
0436 {
0437     u16 wsmc;
0438     struct snd_ad1889 *chip = snd_pcm_substream_chip(ss);
0439     
0440     wsmc = ad1889_readw(chip, AD_DS_WSMC);
0441 
0442     switch (cmd) {
0443     case SNDRV_PCM_TRIGGER_START:
0444         /* enable DMA loop & interrupts */
0445         ad1889_writew(chip, AD_DMA_WAV, AD_DMA_LOOP | AD_DMA_IM_CNT);
0446         wsmc |= AD_DS_WSMC_WAEN;
0447         /* 1 to clear CHSS bit */
0448         ad1889_writel(chip, AD_DMA_CHSS, AD_DMA_CHSS_WAVS);
0449         ad1889_unmute(chip);
0450         break;
0451     case SNDRV_PCM_TRIGGER_STOP:
0452         ad1889_mute(chip);
0453         wsmc &= ~AD_DS_WSMC_WAEN;
0454         break;
0455     default:
0456         snd_BUG();
0457         return -EINVAL;
0458     }
0459     
0460     chip->wave.reg = wsmc;
0461     ad1889_writew(chip, AD_DS_WSMC, wsmc);  
0462     ad1889_readw(chip, AD_DS_WSMC); /* flush */
0463 
0464     /* reset the chip when STOP - will disable IRQs */
0465     if (cmd == SNDRV_PCM_TRIGGER_STOP)
0466         ad1889_channel_reset(chip, AD_CHAN_WAV);
0467 
0468     return 0;
0469 }
0470 
0471 /* this is called in atomic context with IRQ disabled.
0472    Must be as fast as possible and not sleep.
0473    DMA should be *triggered* by this call.
0474    The RAMC "ADEN" bit triggers DMA ADC On/Off */
0475 static int
0476 snd_ad1889_capture_trigger(struct snd_pcm_substream *ss, int cmd)
0477 {
0478     u16 ramc;
0479     struct snd_ad1889 *chip = snd_pcm_substream_chip(ss);
0480 
0481     ramc = ad1889_readw(chip, AD_DS_RAMC);
0482     
0483     switch (cmd) {
0484     case SNDRV_PCM_TRIGGER_START:
0485         /* enable DMA loop & interrupts */
0486         ad1889_writew(chip, AD_DMA_ADC, AD_DMA_LOOP | AD_DMA_IM_CNT);
0487         ramc |= AD_DS_RAMC_ADEN;
0488         /* 1 to clear CHSS bit */
0489         ad1889_writel(chip, AD_DMA_CHSS, AD_DMA_CHSS_ADCS);
0490         break;
0491     case SNDRV_PCM_TRIGGER_STOP:
0492         ramc &= ~AD_DS_RAMC_ADEN;
0493         break;
0494     default:
0495         return -EINVAL;
0496     }
0497     
0498     chip->ramc.reg = ramc;
0499     ad1889_writew(chip, AD_DS_RAMC, ramc);  
0500     ad1889_readw(chip, AD_DS_RAMC); /* flush */
0501     
0502     /* reset the chip when STOP - will disable IRQs */
0503     if (cmd == SNDRV_PCM_TRIGGER_STOP)
0504         ad1889_channel_reset(chip, AD_CHAN_ADC);
0505         
0506     return 0;
0507 }
0508 
0509 /* Called in atomic context with IRQ disabled */
0510 static snd_pcm_uframes_t
0511 snd_ad1889_playback_pointer(struct snd_pcm_substream *ss)
0512 {
0513     size_t ptr = 0;
0514     struct snd_ad1889 *chip = snd_pcm_substream_chip(ss);
0515 
0516     if (unlikely(!(chip->wave.reg & AD_DS_WSMC_WAEN)))
0517         return 0;
0518 
0519     ptr = ad1889_readl(chip, AD_DMA_WAVCA);
0520     ptr -= chip->wave.addr;
0521     
0522     if (snd_BUG_ON(ptr >= chip->wave.size))
0523         return 0;
0524     
0525     return bytes_to_frames(ss->runtime, ptr);
0526 }
0527 
0528 /* Called in atomic context with IRQ disabled */
0529 static snd_pcm_uframes_t
0530 snd_ad1889_capture_pointer(struct snd_pcm_substream *ss)
0531 {
0532     size_t ptr = 0;
0533     struct snd_ad1889 *chip = snd_pcm_substream_chip(ss);
0534 
0535     if (unlikely(!(chip->ramc.reg & AD_DS_RAMC_ADEN)))
0536         return 0;
0537 
0538     ptr = ad1889_readl(chip, AD_DMA_ADCCA);
0539     ptr -= chip->ramc.addr;
0540 
0541     if (snd_BUG_ON(ptr >= chip->ramc.size))
0542         return 0;
0543     
0544     return bytes_to_frames(ss->runtime, ptr);
0545 }
0546 
0547 static const struct snd_pcm_ops snd_ad1889_playback_ops = {
0548     .open = snd_ad1889_playback_open,
0549     .close = snd_ad1889_playback_close,
0550     .prepare = snd_ad1889_playback_prepare,
0551     .trigger = snd_ad1889_playback_trigger,
0552     .pointer = snd_ad1889_playback_pointer, 
0553 };
0554 
0555 static const struct snd_pcm_ops snd_ad1889_capture_ops = {
0556     .open = snd_ad1889_capture_open,
0557     .close = snd_ad1889_capture_close,
0558     .prepare = snd_ad1889_capture_prepare,
0559     .trigger = snd_ad1889_capture_trigger,
0560     .pointer = snd_ad1889_capture_pointer, 
0561 };
0562 
0563 static irqreturn_t
0564 snd_ad1889_interrupt(int irq, void *dev_id)
0565 {
0566     unsigned long st;
0567     struct snd_ad1889 *chip = dev_id;
0568 
0569     st = ad1889_readl(chip, AD_DMA_DISR);
0570 
0571     /* clear ISR */
0572     ad1889_writel(chip, AD_DMA_DISR, st);
0573 
0574     st &= AD_INTR_MASK;
0575 
0576     if (unlikely(!st))
0577         return IRQ_NONE;
0578 
0579     if (st & (AD_DMA_DISR_PMAI|AD_DMA_DISR_PTAI))
0580         dev_dbg(chip->card->dev,
0581             "Unexpected master or target abort interrupt!\n");
0582 
0583     if ((st & AD_DMA_DISR_WAVI) && chip->psubs)
0584         snd_pcm_period_elapsed(chip->psubs);
0585     if ((st & AD_DMA_DISR_ADCI) && chip->csubs)
0586         snd_pcm_period_elapsed(chip->csubs);
0587 
0588     return IRQ_HANDLED;
0589 }
0590 
0591 static int
0592 snd_ad1889_pcm_init(struct snd_ad1889 *chip, int device)
0593 {
0594     int err;
0595     struct snd_pcm *pcm;
0596 
0597     err = snd_pcm_new(chip->card, chip->card->driver, device, 1, 1, &pcm);
0598     if (err < 0)
0599         return err;
0600 
0601     snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, 
0602             &snd_ad1889_playback_ops);
0603     snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
0604             &snd_ad1889_capture_ops);
0605 
0606     pcm->private_data = chip;
0607     pcm->info_flags = 0;
0608     strcpy(pcm->name, chip->card->shortname);
0609     
0610     chip->pcm = pcm;
0611     chip->psubs = NULL;
0612     chip->csubs = NULL;
0613 
0614     snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, &chip->pci->dev,
0615                        BUFFER_BYTES_MAX / 2, BUFFER_BYTES_MAX);
0616 
0617     return 0;
0618 }
0619 
0620 static void
0621 snd_ad1889_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
0622 {
0623     struct snd_ad1889 *chip = entry->private_data;
0624     u16 reg;
0625     int tmp;
0626 
0627     reg = ad1889_readw(chip, AD_DS_WSMC);
0628     snd_iprintf(buffer, "Wave output: %s\n",
0629             (reg & AD_DS_WSMC_WAEN) ? "enabled" : "disabled");
0630     snd_iprintf(buffer, "Wave Channels: %s\n",
0631             (reg & AD_DS_WSMC_WAST) ? "stereo" : "mono");
0632     snd_iprintf(buffer, "Wave Quality: %d-bit linear\n",
0633             (reg & AD_DS_WSMC_WA16) ? 16 : 8);
0634     
0635     /* WARQ is at offset 12 */
0636     tmp = (reg & AD_DS_WSMC_WARQ) ?
0637         ((((reg & AD_DS_WSMC_WARQ) >> 12) & 0x01) ? 12 : 18) : 4;
0638     tmp /= (reg & AD_DS_WSMC_WAST) ? 2 : 1;
0639     
0640     snd_iprintf(buffer, "Wave FIFO: %d %s words\n\n", tmp,
0641             (reg & AD_DS_WSMC_WAST) ? "stereo" : "mono");
0642                 
0643     
0644     snd_iprintf(buffer, "Synthesis output: %s\n",
0645             reg & AD_DS_WSMC_SYEN ? "enabled" : "disabled");
0646     
0647     /* SYRQ is at offset 4 */
0648     tmp = (reg & AD_DS_WSMC_SYRQ) ?
0649         ((((reg & AD_DS_WSMC_SYRQ) >> 4) & 0x01) ? 12 : 18) : 4;
0650     tmp /= (reg & AD_DS_WSMC_WAST) ? 2 : 1;
0651     
0652     snd_iprintf(buffer, "Synthesis FIFO: %d %s words\n\n", tmp,
0653             (reg & AD_DS_WSMC_WAST) ? "stereo" : "mono");
0654 
0655     reg = ad1889_readw(chip, AD_DS_RAMC);
0656     snd_iprintf(buffer, "ADC input: %s\n",
0657             (reg & AD_DS_RAMC_ADEN) ? "enabled" : "disabled");
0658     snd_iprintf(buffer, "ADC Channels: %s\n",
0659             (reg & AD_DS_RAMC_ADST) ? "stereo" : "mono");
0660     snd_iprintf(buffer, "ADC Quality: %d-bit linear\n",
0661             (reg & AD_DS_RAMC_AD16) ? 16 : 8);
0662     
0663     /* ACRQ is at offset 4 */
0664     tmp = (reg & AD_DS_RAMC_ACRQ) ?
0665         ((((reg & AD_DS_RAMC_ACRQ) >> 4) & 0x01) ? 12 : 18) : 4;
0666     tmp /= (reg & AD_DS_RAMC_ADST) ? 2 : 1;
0667     
0668     snd_iprintf(buffer, "ADC FIFO: %d %s words\n\n", tmp,
0669             (reg & AD_DS_RAMC_ADST) ? "stereo" : "mono");
0670     
0671     snd_iprintf(buffer, "Resampler input: %s\n",
0672             reg & AD_DS_RAMC_REEN ? "enabled" : "disabled");
0673             
0674     /* RERQ is at offset 12 */
0675     tmp = (reg & AD_DS_RAMC_RERQ) ?
0676         ((((reg & AD_DS_RAMC_RERQ) >> 12) & 0x01) ? 12 : 18) : 4;
0677     tmp /= (reg & AD_DS_RAMC_ADST) ? 2 : 1;
0678     
0679     snd_iprintf(buffer, "Resampler FIFO: %d %s words\n\n", tmp,
0680             (reg & AD_DS_WSMC_WAST) ? "stereo" : "mono");
0681                 
0682     
0683     /* doc says LSB represents -1.5dB, but the max value (-94.5dB)
0684     suggests that LSB is -3dB, which is more coherent with the logarithmic
0685     nature of the dB scale */
0686     reg = ad1889_readw(chip, AD_DS_WADA);
0687     snd_iprintf(buffer, "Left: %s, -%d dB\n",
0688             (reg & AD_DS_WADA_LWAM) ? "mute" : "unmute",
0689             ((reg & AD_DS_WADA_LWAA) >> 8) * 3);
0690     reg = ad1889_readw(chip, AD_DS_WADA);
0691     snd_iprintf(buffer, "Right: %s, -%d dB\n",
0692             (reg & AD_DS_WADA_RWAM) ? "mute" : "unmute",
0693             (reg & AD_DS_WADA_RWAA) * 3);
0694     
0695     reg = ad1889_readw(chip, AD_DS_WAS);
0696     snd_iprintf(buffer, "Wave samplerate: %u Hz\n", reg);
0697     reg = ad1889_readw(chip, AD_DS_RES);
0698     snd_iprintf(buffer, "Resampler samplerate: %u Hz\n", reg);
0699 }
0700 
0701 static void
0702 snd_ad1889_proc_init(struct snd_ad1889 *chip)
0703 {
0704     snd_card_ro_proc_new(chip->card, chip->card->driver,
0705                  chip, snd_ad1889_proc_read);
0706 }
0707 
0708 static const struct ac97_quirk ac97_quirks[] = {
0709     {
0710         .subvendor = 0x11d4,    /* AD */
0711         .subdevice = 0x1889,    /* AD1889 */
0712         .codec_id = AC97_ID_AD1819,
0713         .name = "AD1889",
0714         .type = AC97_TUNE_HP_ONLY
0715     },
0716     { } /* terminator */
0717 };
0718 
0719 static void
0720 snd_ad1889_ac97_xinit(struct snd_ad1889 *chip)
0721 {
0722     u16 reg;
0723 
0724     reg = ad1889_readw(chip, AD_AC97_ACIC);
0725     reg |= AD_AC97_ACIC_ACRD;       /* Reset Disable */
0726     ad1889_writew(chip, AD_AC97_ACIC, reg);
0727     ad1889_readw(chip, AD_AC97_ACIC);   /* flush posted write */
0728     udelay(10);
0729     /* Interface Enable */
0730     reg |= AD_AC97_ACIC_ACIE;
0731     ad1889_writew(chip, AD_AC97_ACIC, reg);
0732     
0733     snd_ad1889_ac97_ready(chip);
0734 
0735     /* Audio Stream Output | Variable Sample Rate Mode */
0736     reg = ad1889_readw(chip, AD_AC97_ACIC);
0737     reg |= AD_AC97_ACIC_ASOE | AD_AC97_ACIC_VSRM;
0738     ad1889_writew(chip, AD_AC97_ACIC, reg);
0739     ad1889_readw(chip, AD_AC97_ACIC); /* flush posted write */
0740 
0741 }
0742 
0743 static int
0744 snd_ad1889_ac97_init(struct snd_ad1889 *chip, const char *quirk_override)
0745 {
0746     int err;
0747     struct snd_ac97_template ac97;
0748     static const struct snd_ac97_bus_ops ops = {
0749         .write = snd_ad1889_ac97_write,
0750         .read = snd_ad1889_ac97_read,
0751     };
0752 
0753     /* doing that here, it works. */
0754     snd_ad1889_ac97_xinit(chip);
0755 
0756     err = snd_ac97_bus(chip->card, 0, &ops, chip, &chip->ac97_bus);
0757     if (err < 0)
0758         return err;
0759     
0760     memset(&ac97, 0, sizeof(ac97));
0761     ac97.private_data = chip;
0762     ac97.pci = chip->pci;
0763 
0764     err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97);
0765     if (err < 0)
0766         return err;
0767         
0768     snd_ac97_tune_hardware(chip->ac97, ac97_quirks, quirk_override);
0769     
0770     return 0;
0771 }
0772 
0773 static void
0774 snd_ad1889_free(struct snd_card *card)
0775 {
0776     struct snd_ad1889 *chip = card->private_data;
0777 
0778     spin_lock_irq(&chip->lock);
0779 
0780     ad1889_mute(chip);
0781 
0782     /* Turn off interrupt on count and zero DMA registers */
0783     ad1889_channel_reset(chip, AD_CHAN_WAV | AD_CHAN_ADC);
0784 
0785     /* clear DISR. If we don't, we'd better jump off the Eiffel Tower */
0786     ad1889_writel(chip, AD_DMA_DISR, AD_DMA_DISR_PTAI | AD_DMA_DISR_PMAI);
0787     ad1889_readl(chip, AD_DMA_DISR);    /* flush, dammit! */
0788 
0789     spin_unlock_irq(&chip->lock);
0790 }
0791 
0792 static int
0793 snd_ad1889_create(struct snd_card *card, struct pci_dev *pci)
0794 {
0795     struct snd_ad1889 *chip = card->private_data;
0796     int err;
0797 
0798     err = pcim_enable_device(pci);
0799     if (err < 0)
0800         return err;
0801 
0802     /* check PCI availability (32bit DMA) */
0803     if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32))) {
0804         dev_err(card->dev, "error setting 32-bit DMA mask.\n");
0805         return -ENXIO;
0806     }
0807 
0808     chip->card = card;
0809     chip->pci = pci;
0810     chip->irq = -1;
0811 
0812     /* (1) PCI resource allocation */
0813     err = pcim_iomap_regions(pci, 1 << 0, card->driver);
0814     if (err < 0)
0815         return err;
0816 
0817     chip->bar = pci_resource_start(pci, 0);
0818     chip->iobase = pcim_iomap_table(pci)[0];
0819     
0820     pci_set_master(pci);
0821 
0822     spin_lock_init(&chip->lock);    /* only now can we call ad1889_free */
0823 
0824     if (devm_request_irq(&pci->dev, pci->irq, snd_ad1889_interrupt,
0825                  IRQF_SHARED, KBUILD_MODNAME, chip)) {
0826         dev_err(card->dev, "cannot obtain IRQ %d\n", pci->irq);
0827         return -EBUSY;
0828     }
0829 
0830     chip->irq = pci->irq;
0831     card->sync_irq = chip->irq;
0832     card->private_free = snd_ad1889_free;
0833 
0834     /* (2) initialization of the chip hardware */
0835     ad1889_writew(chip, AD_DS_CCS, AD_DS_CCS_CLKEN); /* turn on clock */
0836     ad1889_readw(chip, AD_DS_CCS);  /* flush posted write */
0837 
0838     usleep_range(10000, 11000);
0839 
0840     /* enable Master and Target abort interrupts */
0841     ad1889_writel(chip, AD_DMA_DISR, AD_DMA_DISR_PMAE | AD_DMA_DISR_PTAE);
0842 
0843     return 0;
0844 }
0845 
0846 static int
0847 __snd_ad1889_probe(struct pci_dev *pci,
0848            const struct pci_device_id *pci_id)
0849 {
0850     int err;
0851     static int devno;
0852     struct snd_card *card;
0853     struct snd_ad1889 *chip;
0854 
0855     /* (1) */
0856     if (devno >= SNDRV_CARDS)
0857         return -ENODEV;
0858     if (!enable[devno]) {
0859         devno++;
0860         return -ENOENT;
0861     }
0862 
0863     /* (2) */
0864     err = snd_devm_card_new(&pci->dev, index[devno], id[devno], THIS_MODULE,
0865                 sizeof(*chip), &card);
0866     if (err < 0)
0867         return err;
0868     chip = card->private_data;
0869 
0870     strcpy(card->driver, "AD1889");
0871     strcpy(card->shortname, "Analog Devices AD1889");
0872 
0873     /* (3) */
0874     err = snd_ad1889_create(card, pci);
0875     if (err < 0)
0876         return err;
0877 
0878     /* (4) */
0879     sprintf(card->longname, "%s at 0x%lx irq %i",
0880         card->shortname, chip->bar, chip->irq);
0881 
0882     /* (5) */
0883     /* register AC97 mixer */
0884     err = snd_ad1889_ac97_init(chip, ac97_quirk[devno]);
0885     if (err < 0)
0886         return err;
0887     
0888     err = snd_ad1889_pcm_init(chip, 0);
0889     if (err < 0)
0890         return err;
0891 
0892     /* register proc interface */
0893     snd_ad1889_proc_init(chip);
0894 
0895     /* (6) */
0896     err = snd_card_register(card);
0897     if (err < 0)
0898         return err;
0899 
0900     /* (7) */
0901     pci_set_drvdata(pci, card);
0902 
0903     devno++;
0904     return 0;
0905 }
0906 
0907 static int snd_ad1889_probe(struct pci_dev *pci,
0908                 const struct pci_device_id *pci_id)
0909 {
0910     return snd_card_free_on_error(&pci->dev, __snd_ad1889_probe(pci, pci_id));
0911 }
0912 
0913 static const struct pci_device_id snd_ad1889_ids[] = {
0914     { PCI_DEVICE(PCI_VENDOR_ID_ANALOG_DEVICES, PCI_DEVICE_ID_AD1889JS) },
0915     { 0, },
0916 };
0917 MODULE_DEVICE_TABLE(pci, snd_ad1889_ids);
0918 
0919 static struct pci_driver ad1889_pci_driver = {
0920     .name = KBUILD_MODNAME,
0921     .id_table = snd_ad1889_ids,
0922     .probe = snd_ad1889_probe,
0923 };
0924 
0925 module_pci_driver(ad1889_pci_driver);
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