OSCL-LXR |
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0001 /* SPDX-License-Identifier: GPL-2.0-only */ 0002 #ifndef __HAL2_H 0003 #define __HAL2_H 0004 0005 /* 0006 * Driver for HAL2 sound processors 0007 * Copyright (c) 1999 Ulf Carlsson <ulfc@bun.falkenberg.se> 0008 * Copyright (c) 2001, 2002, 2003 Ladislav Michl <ladis@linux-mips.org> 0009 */ 0010 0011 #include <linux/types.h> 0012 0013 /* Indirect status register */ 0014 0015 #define H2_ISR_TSTATUS 0x01 /* RO: transaction status 1=busy */ 0016 #define H2_ISR_USTATUS 0x02 /* RO: utime status bit 1=armed */ 0017 #define H2_ISR_QUAD_MODE 0x04 /* codec mode 0=indigo 1=quad */ 0018 #define H2_ISR_GLOBAL_RESET_N 0x08 /* chip global reset 0=reset */ 0019 #define H2_ISR_CODEC_RESET_N 0x10 /* codec/synth reset 0=reset */ 0020 0021 /* Revision register */ 0022 0023 #define H2_REV_AUDIO_PRESENT 0x8000 /* RO: audio present 0=present */ 0024 #define H2_REV_BOARD_M 0x7000 /* RO: bits 14:12, board revision */ 0025 #define H2_REV_MAJOR_CHIP_M 0x00F0 /* RO: bits 7:4, major chip revision */ 0026 #define H2_REV_MINOR_CHIP_M 0x000F /* RO: bits 3:0, minor chip revision */ 0027 0028 /* Indirect address register */ 0029 0030 /* 0031 * Address of indirect internal register to be accessed. A write to this 0032 * register initiates read or write access to the indirect registers in the 0033 * HAL2. Note that there af four indirect data registers for write access to 0034 * registers larger than 16 byte. 0035 */ 0036 0037 #define H2_IAR_TYPE_M 0xF000 /* bits 15:12, type of functional */ 0038 /* block the register resides in */ 0039 /* 1=DMA Port */ 0040 /* 9=Global DMA Control */ 0041 /* 2=Bresenham */ 0042 /* 3=Unix Timer */ 0043 #define H2_IAR_NUM_M 0x0F00 /* bits 11:8 instance of the */ 0044 /* blockin which the indirect */ 0045 /* register resides */ 0046 /* If IAR_TYPE_M=DMA Port: */ 0047 /* 1=Synth In */ 0048 /* 2=AES In */ 0049 /* 3=AES Out */ 0050 /* 4=DAC Out */ 0051 /* 5=ADC Out */ 0052 /* 6=Synth Control */ 0053 /* If IAR_TYPE_M=Global DMA Control: */ 0054 /* 1=Control */ 0055 /* If IAR_TYPE_M=Bresenham: */ 0056 /* 1=Bresenham Clock Gen 1 */ 0057 /* 2=Bresenham Clock Gen 2 */ 0058 /* 3=Bresenham Clock Gen 3 */ 0059 /* If IAR_TYPE_M=Unix Timer: */ 0060 /* 1=Unix Timer */ 0061 #define H2_IAR_ACCESS_SELECT 0x0080 /* 1=read 0=write */ 0062 #define H2_IAR_PARAM 0x000C /* Parameter Select */ 0063 #define H2_IAR_RB_INDEX_M 0x0003 /* Read Back Index */ 0064 /* 00:word0 */ 0065 /* 01:word1 */ 0066 /* 10:word2 */ 0067 /* 11:word3 */ 0068 /* 0069 * HAL2 internal addressing 0070 * 0071 * The HAL2 has "indirect registers" (idr) which are accessed by writing to the 0072 * Indirect Data registers. Write the address to the Indirect Address register 0073 * to transfer the data. 0074 * 0075 * We define the H2IR_* to the read address and H2IW_* to the write address and 0076 * H2I_* to be fields in whatever register is referred to. 0077 * 0078 * When we write to indirect registers which are larger than one word (16 bit) 0079 * we have to fill more than one indirect register before writing. When we read 0080 * back however we have to read several times, each time with different Read 0081 * Back Indexes (there are defs for doing this easily). 0082 */ 0083 0084 /* 0085 * Relay Control 0086 */ 0087 #define H2I_RELAY_C 0x9100 0088 #define H2I_RELAY_C_STATE 0x01 /* state of RELAY pin signal */ 0089 0090 /* DMA port enable */ 0091 0092 #define H2I_DMA_PORT_EN 0x9104 0093 #define H2I_DMA_PORT_EN_SY_IN 0x01 /* Synth_in DMA port */ 0094 #define H2I_DMA_PORT_EN_AESRX 0x02 /* AES receiver DMA port */ 0095 #define H2I_DMA_PORT_EN_AESTX 0x04 /* AES transmitter DMA port */ 0096 #define H2I_DMA_PORT_EN_CODECTX 0x08 /* CODEC transmit DMA port */ 0097 #define H2I_DMA_PORT_EN_CODECR 0x10 /* CODEC receive DMA port */ 0098 0099 #define H2I_DMA_END 0x9108 /* global dma endian select */ 0100 #define H2I_DMA_END_SY_IN 0x01 /* Synth_in DMA port */ 0101 #define H2I_DMA_END_AESRX 0x02 /* AES receiver DMA port */ 0102 #define H2I_DMA_END_AESTX 0x04 /* AES transmitter DMA port */ 0103 #define H2I_DMA_END_CODECTX 0x08 /* CODEC transmit DMA port */ 0104 #define H2I_DMA_END_CODECR 0x10 /* CODEC receive DMA port */ 0105 /* 0=b_end 1=l_end */ 0106 0107 #define H2I_DMA_DRV 0x910C /* global PBUS DMA enable */ 0108 0109 #define H2I_SYNTH_C 0x1104 /* Synth DMA control */ 0110 0111 #define H2I_AESRX_C 0x1204 /* AES RX dma control */ 0112 0113 #define H2I_C_TS_EN 0x20 /* Timestamp enable */ 0114 #define H2I_C_TS_FRMT 0x40 /* Timestamp format */ 0115 #define H2I_C_NAUDIO 0x80 /* Sign extend */ 0116 0117 /* AESRX CTL, 16 bit */ 0118 0119 #define H2I_AESTX_C 0x1304 /* AES TX DMA control */ 0120 #define H2I_AESTX_C_CLKID_SHIFT 3 /* Bresenham Clock Gen 1-3 */ 0121 #define H2I_AESTX_C_CLKID_M 0x18 0122 #define H2I_AESTX_C_DATAT_SHIFT 8 /* 1=mono 2=stereo (3=quad) */ 0123 #define H2I_AESTX_C_DATAT_M 0x300 0124 0125 /* CODEC registers */ 0126 0127 #define H2I_DAC_C1 0x1404 /* DAC DMA control, 16 bit */ 0128 #define H2I_DAC_C2 0x1408 /* DAC DMA control, 32 bit */ 0129 #define H2I_ADC_C1 0x1504 /* ADC DMA control, 16 bit */ 0130 #define H2I_ADC_C2 0x1508 /* ADC DMA control, 32 bit */ 0131 0132 /* Bits in CTL1 register */ 0133 0134 #define H2I_C1_DMA_SHIFT 0 /* DMA channel */ 0135 #define H2I_C1_DMA_M 0x7 0136 #define H2I_C1_CLKID_SHIFT 3 /* Bresenham Clock Gen 1-3 */ 0137 #define H2I_C1_CLKID_M 0x18 0138 #define H2I_C1_DATAT_SHIFT 8 /* 1=mono 2=stereo (3=quad) */ 0139 #define H2I_C1_DATAT_M 0x300 0140 0141 /* Bits in CTL2 register */ 0142 0143 #define H2I_C2_R_GAIN_SHIFT 0 /* right a/d input gain */ 0144 #define H2I_C2_R_GAIN_M 0xf 0145 #define H2I_C2_L_GAIN_SHIFT 4 /* left a/d input gain */ 0146 #define H2I_C2_L_GAIN_M 0xf0 0147 #define H2I_C2_R_SEL 0x100 /* right input select */ 0148 #define H2I_C2_L_SEL 0x200 /* left input select */ 0149 #define H2I_C2_MUTE 0x400 /* mute */ 0150 #define H2I_C2_DO1 0x00010000 /* digital output port bit 0 */ 0151 #define H2I_C2_DO2 0x00020000 /* digital output port bit 1 */ 0152 #define H2I_C2_R_ATT_SHIFT 18 /* right d/a output - */ 0153 #define H2I_C2_R_ATT_M 0x007c0000 /* attenuation */ 0154 #define H2I_C2_L_ATT_SHIFT 23 /* left d/a output - */ 0155 #define H2I_C2_L_ATT_M 0x0f800000 /* attenuation */ 0156 0157 #define H2I_SYNTH_MAP_C 0x1104 /* synth dma handshake ctrl */ 0158 0159 /* Clock generator CTL 1, 16 bit */ 0160 0161 #define H2I_BRES1_C1 0x2104 0162 #define H2I_BRES2_C1 0x2204 0163 #define H2I_BRES3_C1 0x2304 0164 0165 #define H2I_BRES_C1_SHIFT 0 /* 0=48.0 1=44.1 2=aes_rx */ 0166 #define H2I_BRES_C1_M 0x03 0167 0168 /* Clock generator CTL 2, 32 bit */ 0169 0170 #define H2I_BRES1_C2 0x2108 0171 #define H2I_BRES2_C2 0x2208 0172 #define H2I_BRES3_C2 0x2308 0173 0174 #define H2I_BRES_C2_INC_SHIFT 0 /* increment value */ 0175 #define H2I_BRES_C2_INC_M 0xffff 0176 #define H2I_BRES_C2_MOD_SHIFT 16 /* modcontrol value */ 0177 #define H2I_BRES_C2_MOD_M 0xffff0000 /* modctrl=0xffff&(modinc-1) */ 0178 0179 /* Unix timer, 64 bit */ 0180 0181 #define H2I_UTIME 0x3104 0182 #define H2I_UTIME_0_LD 0xffff /* microseconds, LSB's */ 0183 #define H2I_UTIME_1_LD0 0x0f /* microseconds, MSB's */ 0184 #define H2I_UTIME_1_LD1 0xf0 /* tenths of microseconds */ 0185 #define H2I_UTIME_2_LD 0xffff /* seconds, LSB's */ 0186 #define H2I_UTIME_3_LD 0xffff /* seconds, MSB's */ 0187 0188 struct hal2_ctl_regs { 0189 u32 _unused0[4]; 0190 u32 isr; /* 0x10 Status Register */ 0191 u32 _unused1[3]; 0192 u32 rev; /* 0x20 Revision Register */ 0193 u32 _unused2[3]; 0194 u32 iar; /* 0x30 Indirect Address Register */ 0195 u32 _unused3[3]; 0196 u32 idr0; /* 0x40 Indirect Data Register 0 */ 0197 u32 _unused4[3]; 0198 u32 idr1; /* 0x50 Indirect Data Register 1 */ 0199 u32 _unused5[3]; 0200 u32 idr2; /* 0x60 Indirect Data Register 2 */ 0201 u32 _unused6[3]; 0202 u32 idr3; /* 0x70 Indirect Data Register 3 */ 0203 }; 0204 0205 struct hal2_aes_regs { 0206 u32 rx_stat[2]; /* Status registers */ 0207 u32 rx_cr[2]; /* Control registers */ 0208 u32 rx_ud[4]; /* User data window */ 0209 u32 rx_st[24]; /* Channel status data */ 0210 0211 u32 tx_stat[1]; /* Status register */ 0212 u32 tx_cr[3]; /* Control registers */ 0213 u32 tx_ud[4]; /* User data window */ 0214 u32 tx_st[24]; /* Channel status data */ 0215 }; 0216 0217 struct hal2_vol_regs { 0218 u32 right; /* Right volume */ 0219 u32 left; /* Left volume */ 0220 }; 0221 0222 struct hal2_syn_regs { 0223 u32 _unused0[2]; 0224 u32 page; /* DOC Page register */ 0225 u32 regsel; /* DOC Register selection */ 0226 u32 dlow; /* DOC Data low */ 0227 u32 dhigh; /* DOC Data high */ 0228 u32 irq; /* IRQ Status */ 0229 u32 dram; /* DRAM Access */ 0230 }; 0231 0232 #endif /* __HAL2_H */
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