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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *  Driver for A2 audio system used in SGI machines
0004  *  Copyright (c) 2008 Thomas Bogendoerfer <tsbogend@alpha.fanken.de>
0005  *
0006  *  Based on OSS code from Ladislav Michl <ladis@linux-mips.org>, which
0007  *  was based on code from Ulf Carlsson
0008  */
0009 #include <linux/kernel.h>
0010 #include <linux/init.h>
0011 #include <linux/interrupt.h>
0012 #include <linux/dma-mapping.h>
0013 #include <linux/platform_device.h>
0014 #include <linux/io.h>
0015 #include <linux/slab.h>
0016 #include <linux/module.h>
0017 
0018 #include <asm/sgi/hpc3.h>
0019 #include <asm/sgi/ip22.h>
0020 
0021 #include <sound/core.h>
0022 #include <sound/control.h>
0023 #include <sound/pcm.h>
0024 #include <sound/pcm-indirect.h>
0025 #include <sound/initval.h>
0026 
0027 #include "hal2.h"
0028 
0029 static int index = SNDRV_DEFAULT_IDX1;  /* Index 0-MAX */
0030 static char *id = SNDRV_DEFAULT_STR1;   /* ID for this card */
0031 
0032 module_param(index, int, 0444);
0033 MODULE_PARM_DESC(index, "Index value for SGI HAL2 soundcard.");
0034 module_param(id, charp, 0444);
0035 MODULE_PARM_DESC(id, "ID string for SGI HAL2 soundcard.");
0036 MODULE_DESCRIPTION("ALSA driver for SGI HAL2 audio");
0037 MODULE_AUTHOR("Thomas Bogendoerfer");
0038 MODULE_LICENSE("GPL");
0039 
0040 
0041 #define H2_BLOCK_SIZE   1024
0042 #define H2_BUF_SIZE 16384
0043 
0044 struct hal2_pbus {
0045     struct hpc3_pbus_dmacregs *pbus;
0046     int pbusnr;
0047     unsigned int ctrl;      /* Current state of pbus->pbdma_ctrl */
0048 };
0049 
0050 struct hal2_desc {
0051     struct hpc_dma_desc desc;
0052     u32 pad;            /* padding */
0053 };
0054 
0055 struct hal2_codec {
0056     struct snd_pcm_indirect pcm_indirect;
0057     struct snd_pcm_substream *substream;
0058 
0059     unsigned char *buffer;
0060     dma_addr_t buffer_dma;
0061     struct hal2_desc *desc;
0062     dma_addr_t desc_dma;
0063     int desc_count;
0064     struct hal2_pbus pbus;
0065     int voices;         /* mono/stereo */
0066     unsigned int sample_rate;
0067     unsigned int master;        /* Master frequency */
0068     unsigned short mod;     /* MOD value */
0069     unsigned short inc;     /* INC value */
0070 };
0071 
0072 #define H2_MIX_OUTPUT_ATT   0
0073 #define H2_MIX_INPUT_GAIN   1
0074 
0075 struct snd_hal2 {
0076     struct snd_card *card;
0077 
0078     struct hal2_ctl_regs *ctl_regs; /* HAL2 ctl registers */
0079     struct hal2_aes_regs *aes_regs; /* HAL2 aes registers */
0080     struct hal2_vol_regs *vol_regs; /* HAL2 vol registers */
0081     struct hal2_syn_regs *syn_regs; /* HAL2 syn registers */
0082 
0083     struct hal2_codec dac;
0084     struct hal2_codec adc;
0085 };
0086 
0087 #define H2_INDIRECT_WAIT(regs)  while (hal2_read(&regs->isr) & H2_ISR_TSTATUS);
0088 
0089 #define H2_READ_ADDR(addr)  (addr | (1<<7))
0090 #define H2_WRITE_ADDR(addr) (addr)
0091 
0092 static inline u32 hal2_read(u32 *reg)
0093 {
0094     return __raw_readl(reg);
0095 }
0096 
0097 static inline void hal2_write(u32 val, u32 *reg)
0098 {
0099     __raw_writel(val, reg);
0100 }
0101 
0102 
0103 static u32 hal2_i_read32(struct snd_hal2 *hal2, u16 addr)
0104 {
0105     u32 ret;
0106     struct hal2_ctl_regs *regs = hal2->ctl_regs;
0107 
0108     hal2_write(H2_READ_ADDR(addr), &regs->iar);
0109     H2_INDIRECT_WAIT(regs);
0110     ret = hal2_read(&regs->idr0) & 0xffff;
0111     hal2_write(H2_READ_ADDR(addr) | 0x1, &regs->iar);
0112     H2_INDIRECT_WAIT(regs);
0113     ret |= (hal2_read(&regs->idr0) & 0xffff) << 16;
0114     return ret;
0115 }
0116 
0117 static void hal2_i_write16(struct snd_hal2 *hal2, u16 addr, u16 val)
0118 {
0119     struct hal2_ctl_regs *regs = hal2->ctl_regs;
0120 
0121     hal2_write(val, &regs->idr0);
0122     hal2_write(0, &regs->idr1);
0123     hal2_write(0, &regs->idr2);
0124     hal2_write(0, &regs->idr3);
0125     hal2_write(H2_WRITE_ADDR(addr), &regs->iar);
0126     H2_INDIRECT_WAIT(regs);
0127 }
0128 
0129 static void hal2_i_write32(struct snd_hal2 *hal2, u16 addr, u32 val)
0130 {
0131     struct hal2_ctl_regs *regs = hal2->ctl_regs;
0132 
0133     hal2_write(val & 0xffff, &regs->idr0);
0134     hal2_write(val >> 16, &regs->idr1);
0135     hal2_write(0, &regs->idr2);
0136     hal2_write(0, &regs->idr3);
0137     hal2_write(H2_WRITE_ADDR(addr), &regs->iar);
0138     H2_INDIRECT_WAIT(regs);
0139 }
0140 
0141 static void hal2_i_setbit16(struct snd_hal2 *hal2, u16 addr, u16 bit)
0142 {
0143     struct hal2_ctl_regs *regs = hal2->ctl_regs;
0144 
0145     hal2_write(H2_READ_ADDR(addr), &regs->iar);
0146     H2_INDIRECT_WAIT(regs);
0147     hal2_write((hal2_read(&regs->idr0) & 0xffff) | bit, &regs->idr0);
0148     hal2_write(0, &regs->idr1);
0149     hal2_write(0, &regs->idr2);
0150     hal2_write(0, &regs->idr3);
0151     hal2_write(H2_WRITE_ADDR(addr), &regs->iar);
0152     H2_INDIRECT_WAIT(regs);
0153 }
0154 
0155 static void hal2_i_clearbit16(struct snd_hal2 *hal2, u16 addr, u16 bit)
0156 {
0157     struct hal2_ctl_regs *regs = hal2->ctl_regs;
0158 
0159     hal2_write(H2_READ_ADDR(addr), &regs->iar);
0160     H2_INDIRECT_WAIT(regs);
0161     hal2_write((hal2_read(&regs->idr0) & 0xffff) & ~bit, &regs->idr0);
0162     hal2_write(0, &regs->idr1);
0163     hal2_write(0, &regs->idr2);
0164     hal2_write(0, &regs->idr3);
0165     hal2_write(H2_WRITE_ADDR(addr), &regs->iar);
0166     H2_INDIRECT_WAIT(regs);
0167 }
0168 
0169 static int hal2_gain_info(struct snd_kcontrol *kcontrol,
0170                    struct snd_ctl_elem_info *uinfo)
0171 {
0172     uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
0173     uinfo->count = 2;
0174     uinfo->value.integer.min = 0;
0175     switch ((int)kcontrol->private_value) {
0176     case H2_MIX_OUTPUT_ATT:
0177         uinfo->value.integer.max = 31;
0178         break;
0179     case H2_MIX_INPUT_GAIN:
0180         uinfo->value.integer.max = 15;
0181         break;
0182     }
0183     return 0;
0184 }
0185 
0186 static int hal2_gain_get(struct snd_kcontrol *kcontrol,
0187                    struct snd_ctl_elem_value *ucontrol)
0188 {
0189     struct snd_hal2 *hal2 = snd_kcontrol_chip(kcontrol);
0190     u32 tmp;
0191     int l, r;
0192 
0193     switch ((int)kcontrol->private_value) {
0194     case H2_MIX_OUTPUT_ATT:
0195         tmp = hal2_i_read32(hal2, H2I_DAC_C2);
0196         if (tmp & H2I_C2_MUTE) {
0197             l = 0;
0198             r = 0;
0199         } else {
0200             l = 31 - ((tmp >> H2I_C2_L_ATT_SHIFT) & 31);
0201             r = 31 - ((tmp >> H2I_C2_R_ATT_SHIFT) & 31);
0202         }
0203         break;
0204     case H2_MIX_INPUT_GAIN:
0205         tmp = hal2_i_read32(hal2, H2I_ADC_C2);
0206         l = (tmp >> H2I_C2_L_GAIN_SHIFT) & 15;
0207         r = (tmp >> H2I_C2_R_GAIN_SHIFT) & 15;
0208         break;
0209     default:
0210         return -EINVAL;
0211     }
0212     ucontrol->value.integer.value[0] = l;
0213     ucontrol->value.integer.value[1] = r;
0214 
0215     return 0;
0216 }
0217 
0218 static int hal2_gain_put(struct snd_kcontrol *kcontrol,
0219              struct snd_ctl_elem_value *ucontrol)
0220 {
0221     struct snd_hal2 *hal2 = snd_kcontrol_chip(kcontrol);
0222     u32 old, new;
0223     int l, r;
0224 
0225     l = ucontrol->value.integer.value[0];
0226     r = ucontrol->value.integer.value[1];
0227 
0228     switch ((int)kcontrol->private_value) {
0229     case H2_MIX_OUTPUT_ATT:
0230         old = hal2_i_read32(hal2, H2I_DAC_C2);
0231         new = old & ~(H2I_C2_L_ATT_M | H2I_C2_R_ATT_M | H2I_C2_MUTE);
0232         if (l | r) {
0233             l = 31 - l;
0234             r = 31 - r;
0235             new |= (l << H2I_C2_L_ATT_SHIFT);
0236             new |= (r << H2I_C2_R_ATT_SHIFT);
0237         } else
0238             new |= H2I_C2_L_ATT_M | H2I_C2_R_ATT_M | H2I_C2_MUTE;
0239         hal2_i_write32(hal2, H2I_DAC_C2, new);
0240         break;
0241     case H2_MIX_INPUT_GAIN:
0242         old = hal2_i_read32(hal2, H2I_ADC_C2);
0243         new = old & ~(H2I_C2_L_GAIN_M | H2I_C2_R_GAIN_M);
0244         new |= (l << H2I_C2_L_GAIN_SHIFT);
0245         new |= (r << H2I_C2_R_GAIN_SHIFT);
0246         hal2_i_write32(hal2, H2I_ADC_C2, new);
0247         break;
0248     default:
0249         return -EINVAL;
0250     }
0251     return old != new;
0252 }
0253 
0254 static const struct snd_kcontrol_new hal2_ctrl_headphone = {
0255     .iface          = SNDRV_CTL_ELEM_IFACE_MIXER,
0256     .name           = "Headphone Playback Volume",
0257     .access         = SNDRV_CTL_ELEM_ACCESS_READWRITE,
0258     .private_value  = H2_MIX_OUTPUT_ATT,
0259     .info           = hal2_gain_info,
0260     .get            = hal2_gain_get,
0261     .put            = hal2_gain_put,
0262 };
0263 
0264 static const struct snd_kcontrol_new hal2_ctrl_mic = {
0265     .iface          = SNDRV_CTL_ELEM_IFACE_MIXER,
0266     .name           = "Mic Capture Volume",
0267     .access         = SNDRV_CTL_ELEM_ACCESS_READWRITE,
0268     .private_value  = H2_MIX_INPUT_GAIN,
0269     .info           = hal2_gain_info,
0270     .get            = hal2_gain_get,
0271     .put            = hal2_gain_put,
0272 };
0273 
0274 static int hal2_mixer_create(struct snd_hal2 *hal2)
0275 {
0276     int err;
0277 
0278     /* mute DAC */
0279     hal2_i_write32(hal2, H2I_DAC_C2,
0280                H2I_C2_L_ATT_M | H2I_C2_R_ATT_M | H2I_C2_MUTE);
0281     /* mute ADC */
0282     hal2_i_write32(hal2, H2I_ADC_C2, 0);
0283 
0284     err = snd_ctl_add(hal2->card,
0285               snd_ctl_new1(&hal2_ctrl_headphone, hal2));
0286     if (err < 0)
0287         return err;
0288 
0289     err = snd_ctl_add(hal2->card,
0290               snd_ctl_new1(&hal2_ctrl_mic, hal2));
0291     if (err < 0)
0292         return err;
0293 
0294     return 0;
0295 }
0296 
0297 static irqreturn_t hal2_interrupt(int irq, void *dev_id)
0298 {
0299     struct snd_hal2 *hal2 = dev_id;
0300     irqreturn_t ret = IRQ_NONE;
0301 
0302     /* decide what caused this interrupt */
0303     if (hal2->dac.pbus.pbus->pbdma_ctrl & HPC3_PDMACTRL_INT) {
0304         snd_pcm_period_elapsed(hal2->dac.substream);
0305         ret = IRQ_HANDLED;
0306     }
0307     if (hal2->adc.pbus.pbus->pbdma_ctrl & HPC3_PDMACTRL_INT) {
0308         snd_pcm_period_elapsed(hal2->adc.substream);
0309         ret = IRQ_HANDLED;
0310     }
0311     return ret;
0312 }
0313 
0314 static int hal2_compute_rate(struct hal2_codec *codec, unsigned int rate)
0315 {
0316     unsigned short mod;
0317 
0318     if (44100 % rate < 48000 % rate) {
0319         mod = 4 * 44100 / rate;
0320         codec->master = 44100;
0321     } else {
0322         mod = 4 * 48000 / rate;
0323         codec->master = 48000;
0324     }
0325 
0326     codec->inc = 4;
0327     codec->mod = mod;
0328     rate = 4 * codec->master / mod;
0329 
0330     return rate;
0331 }
0332 
0333 static void hal2_set_dac_rate(struct snd_hal2 *hal2)
0334 {
0335     unsigned int master = hal2->dac.master;
0336     int inc = hal2->dac.inc;
0337     int mod = hal2->dac.mod;
0338 
0339     hal2_i_write16(hal2, H2I_BRES1_C1, (master == 44100) ? 1 : 0);
0340     hal2_i_write32(hal2, H2I_BRES1_C2,
0341                ((0xffff & (inc - mod - 1)) << 16) | inc);
0342 }
0343 
0344 static void hal2_set_adc_rate(struct snd_hal2 *hal2)
0345 {
0346     unsigned int master = hal2->adc.master;
0347     int inc = hal2->adc.inc;
0348     int mod = hal2->adc.mod;
0349 
0350     hal2_i_write16(hal2, H2I_BRES2_C1, (master == 44100) ? 1 : 0);
0351     hal2_i_write32(hal2, H2I_BRES2_C2,
0352                ((0xffff & (inc - mod - 1)) << 16) | inc);
0353 }
0354 
0355 static void hal2_setup_dac(struct snd_hal2 *hal2)
0356 {
0357     unsigned int fifobeg, fifoend, highwater, sample_size;
0358     struct hal2_pbus *pbus = &hal2->dac.pbus;
0359 
0360     /* Now we set up some PBUS information. The PBUS needs information about
0361      * what portion of the fifo it will use. If it's receiving or
0362      * transmitting, and finally whether the stream is little endian or big
0363      * endian. The information is written later, on the start call.
0364      */
0365     sample_size = 2 * hal2->dac.voices;
0366     /* Fifo should be set to hold exactly four samples. Highwater mark
0367      * should be set to two samples. */
0368     highwater = (sample_size * 2) >> 1; /* halfwords */
0369     fifobeg = 0;                /* playback is first */
0370     fifoend = (sample_size * 4) >> 3;   /* doublewords */
0371     pbus->ctrl = HPC3_PDMACTRL_RT | HPC3_PDMACTRL_LD |
0372              (highwater << 8) | (fifobeg << 16) | (fifoend << 24);
0373     /* We disable everything before we do anything at all */
0374     pbus->pbus->pbdma_ctrl = HPC3_PDMACTRL_LD;
0375     hal2_i_clearbit16(hal2, H2I_DMA_PORT_EN, H2I_DMA_PORT_EN_CODECTX);
0376     /* Setup the HAL2 for playback */
0377     hal2_set_dac_rate(hal2);
0378     /* Set endianess */
0379     hal2_i_clearbit16(hal2, H2I_DMA_END, H2I_DMA_END_CODECTX);
0380     /* Set DMA bus */
0381     hal2_i_setbit16(hal2, H2I_DMA_DRV, (1 << pbus->pbusnr));
0382     /* We are using 1st Bresenham clock generator for playback */
0383     hal2_i_write16(hal2, H2I_DAC_C1, (pbus->pbusnr << H2I_C1_DMA_SHIFT)
0384             | (1 << H2I_C1_CLKID_SHIFT)
0385             | (hal2->dac.voices << H2I_C1_DATAT_SHIFT));
0386 }
0387 
0388 static void hal2_setup_adc(struct snd_hal2 *hal2)
0389 {
0390     unsigned int fifobeg, fifoend, highwater, sample_size;
0391     struct hal2_pbus *pbus = &hal2->adc.pbus;
0392 
0393     sample_size = 2 * hal2->adc.voices;
0394     highwater = (sample_size * 2) >> 1;     /* halfwords */
0395     fifobeg = (4 * 4) >> 3;             /* record is second */
0396     fifoend = (4 * 4 + sample_size * 4) >> 3;   /* doublewords */
0397     pbus->ctrl = HPC3_PDMACTRL_RT | HPC3_PDMACTRL_RCV | HPC3_PDMACTRL_LD |
0398              (highwater << 8) | (fifobeg << 16) | (fifoend << 24);
0399     pbus->pbus->pbdma_ctrl = HPC3_PDMACTRL_LD;
0400     hal2_i_clearbit16(hal2, H2I_DMA_PORT_EN, H2I_DMA_PORT_EN_CODECR);
0401     /* Setup the HAL2 for record */
0402     hal2_set_adc_rate(hal2);
0403     /* Set endianess */
0404     hal2_i_clearbit16(hal2, H2I_DMA_END, H2I_DMA_END_CODECR);
0405     /* Set DMA bus */
0406     hal2_i_setbit16(hal2, H2I_DMA_DRV, (1 << pbus->pbusnr));
0407     /* We are using 2nd Bresenham clock generator for record */
0408     hal2_i_write16(hal2, H2I_ADC_C1, (pbus->pbusnr << H2I_C1_DMA_SHIFT)
0409             | (2 << H2I_C1_CLKID_SHIFT)
0410             | (hal2->adc.voices << H2I_C1_DATAT_SHIFT));
0411 }
0412 
0413 static void hal2_start_dac(struct snd_hal2 *hal2)
0414 {
0415     struct hal2_pbus *pbus = &hal2->dac.pbus;
0416 
0417     pbus->pbus->pbdma_dptr = hal2->dac.desc_dma;
0418     pbus->pbus->pbdma_ctrl = pbus->ctrl | HPC3_PDMACTRL_ACT;
0419     /* enable DAC */
0420     hal2_i_setbit16(hal2, H2I_DMA_PORT_EN, H2I_DMA_PORT_EN_CODECTX);
0421 }
0422 
0423 static void hal2_start_adc(struct snd_hal2 *hal2)
0424 {
0425     struct hal2_pbus *pbus = &hal2->adc.pbus;
0426 
0427     pbus->pbus->pbdma_dptr = hal2->adc.desc_dma;
0428     pbus->pbus->pbdma_ctrl = pbus->ctrl | HPC3_PDMACTRL_ACT;
0429     /* enable ADC */
0430     hal2_i_setbit16(hal2, H2I_DMA_PORT_EN, H2I_DMA_PORT_EN_CODECR);
0431 }
0432 
0433 static inline void hal2_stop_dac(struct snd_hal2 *hal2)
0434 {
0435     hal2->dac.pbus.pbus->pbdma_ctrl = HPC3_PDMACTRL_LD;
0436     /* The HAL2 itself may remain enabled safely */
0437 }
0438 
0439 static inline void hal2_stop_adc(struct snd_hal2 *hal2)
0440 {
0441     hal2->adc.pbus.pbus->pbdma_ctrl = HPC3_PDMACTRL_LD;
0442 }
0443 
0444 static int hal2_alloc_dmabuf(struct snd_hal2 *hal2, struct hal2_codec *codec,
0445         enum dma_data_direction buffer_dir)
0446 {
0447     struct device *dev = hal2->card->dev;
0448     struct hal2_desc *desc;
0449     dma_addr_t desc_dma, buffer_dma;
0450     int count = H2_BUF_SIZE / H2_BLOCK_SIZE;
0451     int i;
0452 
0453     codec->buffer = dma_alloc_noncoherent(dev, H2_BUF_SIZE, &buffer_dma,
0454                     buffer_dir, GFP_KERNEL);
0455     if (!codec->buffer)
0456         return -ENOMEM;
0457     desc = dma_alloc_noncoherent(dev, count * sizeof(struct hal2_desc),
0458             &desc_dma, DMA_BIDIRECTIONAL, GFP_KERNEL);
0459     if (!desc) {
0460         dma_free_noncoherent(dev, H2_BUF_SIZE, codec->buffer, buffer_dma,
0461                 buffer_dir);
0462         return -ENOMEM;
0463     }
0464     codec->buffer_dma = buffer_dma;
0465     codec->desc_dma = desc_dma;
0466     codec->desc = desc;
0467     for (i = 0; i < count; i++) {
0468         desc->desc.pbuf = buffer_dma + i * H2_BLOCK_SIZE;
0469         desc->desc.cntinfo = HPCDMA_XIE | H2_BLOCK_SIZE;
0470         desc->desc.pnext = (i == count - 1) ?
0471               desc_dma : desc_dma + (i + 1) * sizeof(struct hal2_desc);
0472         desc++;
0473     }
0474     dma_sync_single_for_device(dev, codec->desc_dma,
0475                    count * sizeof(struct hal2_desc),
0476                    DMA_BIDIRECTIONAL);
0477     codec->desc_count = count;
0478     return 0;
0479 }
0480 
0481 static void hal2_free_dmabuf(struct snd_hal2 *hal2, struct hal2_codec *codec,
0482         enum dma_data_direction buffer_dir)
0483 {
0484     struct device *dev = hal2->card->dev;
0485 
0486     dma_free_noncoherent(dev, codec->desc_count * sizeof(struct hal2_desc),
0487                codec->desc, codec->desc_dma, DMA_BIDIRECTIONAL);
0488     dma_free_noncoherent(dev, H2_BUF_SIZE, codec->buffer, codec->buffer_dma,
0489             buffer_dir);
0490 }
0491 
0492 static const struct snd_pcm_hardware hal2_pcm_hw = {
0493     .info = (SNDRV_PCM_INFO_MMAP |
0494          SNDRV_PCM_INFO_MMAP_VALID |
0495          SNDRV_PCM_INFO_INTERLEAVED |
0496          SNDRV_PCM_INFO_BLOCK_TRANSFER |
0497          SNDRV_PCM_INFO_SYNC_APPLPTR),
0498     .formats =          SNDRV_PCM_FMTBIT_S16_BE,
0499     .rates =            SNDRV_PCM_RATE_8000_48000,
0500     .rate_min =         8000,
0501     .rate_max =         48000,
0502     .channels_min =     2,
0503     .channels_max =     2,
0504     .buffer_bytes_max = 65536,
0505     .period_bytes_min = 1024,
0506     .period_bytes_max = 65536,
0507     .periods_min =      2,
0508     .periods_max =      1024,
0509 };
0510 
0511 static int hal2_playback_open(struct snd_pcm_substream *substream)
0512 {
0513     struct snd_pcm_runtime *runtime = substream->runtime;
0514     struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
0515 
0516     runtime->hw = hal2_pcm_hw;
0517     return hal2_alloc_dmabuf(hal2, &hal2->dac, DMA_TO_DEVICE);
0518 }
0519 
0520 static int hal2_playback_close(struct snd_pcm_substream *substream)
0521 {
0522     struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
0523 
0524     hal2_free_dmabuf(hal2, &hal2->dac, DMA_TO_DEVICE);
0525     return 0;
0526 }
0527 
0528 static int hal2_playback_prepare(struct snd_pcm_substream *substream)
0529 {
0530     struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
0531     struct snd_pcm_runtime *runtime = substream->runtime;
0532     struct hal2_codec *dac = &hal2->dac;
0533 
0534     dac->voices = runtime->channels;
0535     dac->sample_rate = hal2_compute_rate(dac, runtime->rate);
0536     memset(&dac->pcm_indirect, 0, sizeof(dac->pcm_indirect));
0537     dac->pcm_indirect.hw_buffer_size = H2_BUF_SIZE;
0538     dac->pcm_indirect.hw_queue_size = H2_BUF_SIZE / 2;
0539     dac->pcm_indirect.hw_io = dac->buffer_dma;
0540     dac->pcm_indirect.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
0541     dac->substream = substream;
0542     hal2_setup_dac(hal2);
0543     return 0;
0544 }
0545 
0546 static int hal2_playback_trigger(struct snd_pcm_substream *substream, int cmd)
0547 {
0548     struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
0549 
0550     switch (cmd) {
0551     case SNDRV_PCM_TRIGGER_START:
0552         hal2_start_dac(hal2);
0553         break;
0554     case SNDRV_PCM_TRIGGER_STOP:
0555         hal2_stop_dac(hal2);
0556         break;
0557     default:
0558         return -EINVAL;
0559     }
0560     return 0;
0561 }
0562 
0563 static snd_pcm_uframes_t
0564 hal2_playback_pointer(struct snd_pcm_substream *substream)
0565 {
0566     struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
0567     struct hal2_codec *dac = &hal2->dac;
0568 
0569     return snd_pcm_indirect_playback_pointer(substream, &dac->pcm_indirect,
0570                          dac->pbus.pbus->pbdma_bptr);
0571 }
0572 
0573 static void hal2_playback_transfer(struct snd_pcm_substream *substream,
0574                    struct snd_pcm_indirect *rec, size_t bytes)
0575 {
0576     struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
0577     unsigned char *buf = hal2->dac.buffer + rec->hw_data;
0578 
0579     memcpy(buf, substream->runtime->dma_area + rec->sw_data, bytes);
0580     dma_sync_single_for_device(hal2->card->dev,
0581             hal2->dac.buffer_dma + rec->hw_data, bytes,
0582             DMA_TO_DEVICE);
0583 
0584 }
0585 
0586 static int hal2_playback_ack(struct snd_pcm_substream *substream)
0587 {
0588     struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
0589     struct hal2_codec *dac = &hal2->dac;
0590 
0591     return snd_pcm_indirect_playback_transfer(substream,
0592                           &dac->pcm_indirect,
0593                           hal2_playback_transfer);
0594 }
0595 
0596 static int hal2_capture_open(struct snd_pcm_substream *substream)
0597 {
0598     struct snd_pcm_runtime *runtime = substream->runtime;
0599     struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
0600 
0601     runtime->hw = hal2_pcm_hw;
0602     return hal2_alloc_dmabuf(hal2, &hal2->adc, DMA_FROM_DEVICE);
0603 }
0604 
0605 static int hal2_capture_close(struct snd_pcm_substream *substream)
0606 {
0607     struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
0608 
0609     hal2_free_dmabuf(hal2, &hal2->adc, DMA_FROM_DEVICE);
0610     return 0;
0611 }
0612 
0613 static int hal2_capture_prepare(struct snd_pcm_substream *substream)
0614 {
0615     struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
0616     struct snd_pcm_runtime *runtime = substream->runtime;
0617     struct hal2_codec *adc = &hal2->adc;
0618 
0619     adc->voices = runtime->channels;
0620     adc->sample_rate = hal2_compute_rate(adc, runtime->rate);
0621     memset(&adc->pcm_indirect, 0, sizeof(adc->pcm_indirect));
0622     adc->pcm_indirect.hw_buffer_size = H2_BUF_SIZE;
0623     adc->pcm_indirect.hw_queue_size = H2_BUF_SIZE / 2;
0624     adc->pcm_indirect.hw_io = adc->buffer_dma;
0625     adc->pcm_indirect.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
0626     adc->substream = substream;
0627     hal2_setup_adc(hal2);
0628     return 0;
0629 }
0630 
0631 static int hal2_capture_trigger(struct snd_pcm_substream *substream, int cmd)
0632 {
0633     struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
0634 
0635     switch (cmd) {
0636     case SNDRV_PCM_TRIGGER_START:
0637         hal2_start_adc(hal2);
0638         break;
0639     case SNDRV_PCM_TRIGGER_STOP:
0640         hal2_stop_adc(hal2);
0641         break;
0642     default:
0643         return -EINVAL;
0644     }
0645     return 0;
0646 }
0647 
0648 static snd_pcm_uframes_t
0649 hal2_capture_pointer(struct snd_pcm_substream *substream)
0650 {
0651     struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
0652     struct hal2_codec *adc = &hal2->adc;
0653 
0654     return snd_pcm_indirect_capture_pointer(substream, &adc->pcm_indirect,
0655                         adc->pbus.pbus->pbdma_bptr);
0656 }
0657 
0658 static void hal2_capture_transfer(struct snd_pcm_substream *substream,
0659                   struct snd_pcm_indirect *rec, size_t bytes)
0660 {
0661     struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
0662     unsigned char *buf = hal2->adc.buffer + rec->hw_data;
0663 
0664     dma_sync_single_for_cpu(hal2->card->dev,
0665             hal2->adc.buffer_dma + rec->hw_data, bytes,
0666             DMA_FROM_DEVICE);
0667     memcpy(substream->runtime->dma_area + rec->sw_data, buf, bytes);
0668 }
0669 
0670 static int hal2_capture_ack(struct snd_pcm_substream *substream)
0671 {
0672     struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
0673     struct hal2_codec *adc = &hal2->adc;
0674 
0675     return snd_pcm_indirect_capture_transfer(substream,
0676                          &adc->pcm_indirect,
0677                          hal2_capture_transfer);
0678 }
0679 
0680 static const struct snd_pcm_ops hal2_playback_ops = {
0681     .open =        hal2_playback_open,
0682     .close =       hal2_playback_close,
0683     .prepare =     hal2_playback_prepare,
0684     .trigger =     hal2_playback_trigger,
0685     .pointer =     hal2_playback_pointer,
0686     .ack =         hal2_playback_ack,
0687 };
0688 
0689 static const struct snd_pcm_ops hal2_capture_ops = {
0690     .open =        hal2_capture_open,
0691     .close =       hal2_capture_close,
0692     .prepare =     hal2_capture_prepare,
0693     .trigger =     hal2_capture_trigger,
0694     .pointer =     hal2_capture_pointer,
0695     .ack =         hal2_capture_ack,
0696 };
0697 
0698 static int hal2_pcm_create(struct snd_hal2 *hal2)
0699 {
0700     struct snd_pcm *pcm;
0701     int err;
0702 
0703     /* create first pcm device with one outputs and one input */
0704     err = snd_pcm_new(hal2->card, "SGI HAL2 Audio", 0, 1, 1, &pcm);
0705     if (err < 0)
0706         return err;
0707 
0708     pcm->private_data = hal2;
0709     strcpy(pcm->name, "SGI HAL2");
0710 
0711     /* set operators */
0712     snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
0713             &hal2_playback_ops);
0714     snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
0715             &hal2_capture_ops);
0716     snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_CONTINUOUS,
0717                        NULL, 0, 1024 * 1024);
0718 
0719     return 0;
0720 }
0721 
0722 static int hal2_dev_free(struct snd_device *device)
0723 {
0724     struct snd_hal2 *hal2 = device->device_data;
0725 
0726     free_irq(SGI_HPCDMA_IRQ, hal2);
0727     kfree(hal2);
0728     return 0;
0729 }
0730 
0731 static const struct snd_device_ops hal2_ops = {
0732     .dev_free = hal2_dev_free,
0733 };
0734 
0735 static void hal2_init_codec(struct hal2_codec *codec, struct hpc3_regs *hpc3,
0736                 int index)
0737 {
0738     codec->pbus.pbusnr = index;
0739     codec->pbus.pbus = &hpc3->pbdma[index];
0740 }
0741 
0742 static int hal2_detect(struct snd_hal2 *hal2)
0743 {
0744     unsigned short board, major, minor;
0745     unsigned short rev;
0746 
0747     /* reset HAL2 */
0748     hal2_write(0, &hal2->ctl_regs->isr);
0749 
0750     /* release reset */
0751     hal2_write(H2_ISR_GLOBAL_RESET_N | H2_ISR_CODEC_RESET_N,
0752            &hal2->ctl_regs->isr);
0753 
0754 
0755     hal2_i_write16(hal2, H2I_RELAY_C, H2I_RELAY_C_STATE);
0756     rev = hal2_read(&hal2->ctl_regs->rev);
0757     if (rev & H2_REV_AUDIO_PRESENT)
0758         return -ENODEV;
0759 
0760     board = (rev & H2_REV_BOARD_M) >> 12;
0761     major = (rev & H2_REV_MAJOR_CHIP_M) >> 4;
0762     minor = (rev & H2_REV_MINOR_CHIP_M);
0763 
0764     printk(KERN_INFO "SGI HAL2 revision %i.%i.%i\n",
0765            board, major, minor);
0766 
0767     return 0;
0768 }
0769 
0770 static int hal2_create(struct snd_card *card, struct snd_hal2 **rchip)
0771 {
0772     struct snd_hal2 *hal2;
0773     struct hpc3_regs *hpc3 = hpc3c0;
0774     int err;
0775 
0776     hal2 = kzalloc(sizeof(*hal2), GFP_KERNEL);
0777     if (!hal2)
0778         return -ENOMEM;
0779 
0780     hal2->card = card;
0781 
0782     if (request_irq(SGI_HPCDMA_IRQ, hal2_interrupt, IRQF_SHARED,
0783             "SGI HAL2", hal2)) {
0784         printk(KERN_ERR "HAL2: Can't get irq %d\n", SGI_HPCDMA_IRQ);
0785         kfree(hal2);
0786         return -EAGAIN;
0787     }
0788 
0789     hal2->ctl_regs = (struct hal2_ctl_regs *)hpc3->pbus_extregs[0];
0790     hal2->aes_regs = (struct hal2_aes_regs *)hpc3->pbus_extregs[1];
0791     hal2->vol_regs = (struct hal2_vol_regs *)hpc3->pbus_extregs[2];
0792     hal2->syn_regs = (struct hal2_syn_regs *)hpc3->pbus_extregs[3];
0793 
0794     if (hal2_detect(hal2) < 0) {
0795         kfree(hal2);
0796         return -ENODEV;
0797     }
0798 
0799     hal2_init_codec(&hal2->dac, hpc3, 0);
0800     hal2_init_codec(&hal2->adc, hpc3, 1);
0801 
0802     /*
0803      * All DMA channel interfaces in HAL2 are designed to operate with
0804      * PBUS programmed for 2 cycles in D3, 2 cycles in D4 and 2 cycles
0805      * in D5. HAL2 is a 16-bit device which can accept both big and little
0806      * endian format. It assumes that even address bytes are on high
0807      * portion of PBUS (15:8) and assumes that HPC3 is programmed to
0808      * accept a live (unsynchronized) version of P_DREQ_N from HAL2.
0809      */
0810 #define HAL2_PBUS_DMACFG ((0 << HPC3_DMACFG_D3R_SHIFT) | \
0811               (2 << HPC3_DMACFG_D4R_SHIFT) | \
0812               (2 << HPC3_DMACFG_D5R_SHIFT) | \
0813               (0 << HPC3_DMACFG_D3W_SHIFT) | \
0814               (2 << HPC3_DMACFG_D4W_SHIFT) | \
0815               (2 << HPC3_DMACFG_D5W_SHIFT) | \
0816                 HPC3_DMACFG_DS16 | \
0817                 HPC3_DMACFG_EVENHI | \
0818                 HPC3_DMACFG_RTIME | \
0819               (8 << HPC3_DMACFG_BURST_SHIFT) | \
0820                 HPC3_DMACFG_DRQLIVE)
0821     /*
0822      * Ignore what's mentioned in the specification and write value which
0823      * works in The Real World (TM)
0824      */
0825     hpc3->pbus_dmacfg[hal2->dac.pbus.pbusnr][0] = 0x8208844;
0826     hpc3->pbus_dmacfg[hal2->adc.pbus.pbusnr][0] = 0x8208844;
0827 
0828     err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, hal2, &hal2_ops);
0829     if (err < 0) {
0830         free_irq(SGI_HPCDMA_IRQ, hal2);
0831         kfree(hal2);
0832         return err;
0833     }
0834     *rchip = hal2;
0835     return 0;
0836 }
0837 
0838 static int hal2_probe(struct platform_device *pdev)
0839 {
0840     struct snd_card *card;
0841     struct snd_hal2 *chip;
0842     int err;
0843 
0844     err = snd_card_new(&pdev->dev, index, id, THIS_MODULE, 0, &card);
0845     if (err < 0)
0846         return err;
0847 
0848     err = hal2_create(card, &chip);
0849     if (err < 0) {
0850         snd_card_free(card);
0851         return err;
0852     }
0853 
0854     err = hal2_pcm_create(chip);
0855     if (err < 0) {
0856         snd_card_free(card);
0857         return err;
0858     }
0859     err = hal2_mixer_create(chip);
0860     if (err < 0) {
0861         snd_card_free(card);
0862         return err;
0863     }
0864 
0865     strcpy(card->driver, "SGI HAL2 Audio");
0866     strcpy(card->shortname, "SGI HAL2 Audio");
0867     sprintf(card->longname, "%s irq %i",
0868         card->shortname,
0869         SGI_HPCDMA_IRQ);
0870 
0871     err = snd_card_register(card);
0872     if (err < 0) {
0873         snd_card_free(card);
0874         return err;
0875     }
0876     platform_set_drvdata(pdev, card);
0877     return 0;
0878 }
0879 
0880 static int hal2_remove(struct platform_device *pdev)
0881 {
0882     struct snd_card *card = platform_get_drvdata(pdev);
0883 
0884     snd_card_free(card);
0885     return 0;
0886 }
0887 
0888 static struct platform_driver hal2_driver = {
0889     .probe  = hal2_probe,
0890     .remove = hal2_remove,
0891     .driver = {
0892         .name   = "sgihal2",
0893     }
0894 };
0895 
0896 module_platform_driver(hal2_driver);
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