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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *  Routines for control of the AK4117 via 4-wire serial interface
0004  *  IEC958 (S/PDIF) receiver by Asahi Kasei
0005  *  Copyright (c) by Jaroslav Kysela <perex@perex.cz>
0006  */
0007 
0008 #include <linux/slab.h>
0009 #include <linux/delay.h>
0010 #include <linux/module.h>
0011 #include <sound/core.h>
0012 #include <sound/control.h>
0013 #include <sound/pcm.h>
0014 #include <sound/ak4117.h>
0015 #include <sound/asoundef.h>
0016 
0017 MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
0018 MODULE_DESCRIPTION("AK4117 IEC958 (S/PDIF) receiver by Asahi Kasei");
0019 MODULE_LICENSE("GPL");
0020 
0021 #define AK4117_ADDR         0x00 /* fixed address */
0022 
0023 static void snd_ak4117_timer(struct timer_list *t);
0024 
0025 static void reg_write(struct ak4117 *ak4117, unsigned char reg, unsigned char val)
0026 {
0027     ak4117->write(ak4117->private_data, reg, val);
0028     if (reg < sizeof(ak4117->regmap))
0029         ak4117->regmap[reg] = val;
0030 }
0031 
0032 static inline unsigned char reg_read(struct ak4117 *ak4117, unsigned char reg)
0033 {
0034     return ak4117->read(ak4117->private_data, reg);
0035 }
0036 
0037 #if 0
0038 static void reg_dump(struct ak4117 *ak4117)
0039 {
0040     int i;
0041 
0042     printk(KERN_DEBUG "AK4117 REG DUMP:\n");
0043     for (i = 0; i < 0x1b; i++)
0044         printk(KERN_DEBUG "reg[%02x] = %02x (%02x)\n", i, reg_read(ak4117, i), i < sizeof(ak4117->regmap) ? ak4117->regmap[i] : 0);
0045 }
0046 #endif
0047 
0048 static void snd_ak4117_free(struct ak4117 *chip)
0049 {
0050     del_timer_sync(&chip->timer);
0051     kfree(chip);
0052 }
0053 
0054 static int snd_ak4117_dev_free(struct snd_device *device)
0055 {
0056     struct ak4117 *chip = device->device_data;
0057     snd_ak4117_free(chip);
0058     return 0;
0059 }
0060 
0061 int snd_ak4117_create(struct snd_card *card, ak4117_read_t *read, ak4117_write_t *write,
0062               const unsigned char pgm[5], void *private_data, struct ak4117 **r_ak4117)
0063 {
0064     struct ak4117 *chip;
0065     int err = 0;
0066     unsigned char reg;
0067     static const struct snd_device_ops ops = {
0068         .dev_free =     snd_ak4117_dev_free,
0069     };
0070 
0071     chip = kzalloc(sizeof(*chip), GFP_KERNEL);
0072     if (chip == NULL)
0073         return -ENOMEM;
0074     spin_lock_init(&chip->lock);
0075     chip->card = card;
0076     chip->read = read;
0077     chip->write = write;
0078     chip->private_data = private_data;
0079     timer_setup(&chip->timer, snd_ak4117_timer, 0);
0080 
0081     for (reg = 0; reg < 5; reg++)
0082         chip->regmap[reg] = pgm[reg];
0083     snd_ak4117_reinit(chip);
0084 
0085     chip->rcs0 = reg_read(chip, AK4117_REG_RCS0) & ~(AK4117_QINT | AK4117_CINT | AK4117_STC);
0086     chip->rcs1 = reg_read(chip, AK4117_REG_RCS1);
0087     chip->rcs2 = reg_read(chip, AK4117_REG_RCS2);
0088 
0089     err = snd_device_new(card, SNDRV_DEV_CODEC, chip, &ops);
0090     if (err < 0)
0091         goto __fail;
0092 
0093     if (r_ak4117)
0094         *r_ak4117 = chip;
0095     return 0;
0096 
0097       __fail:
0098     snd_ak4117_free(chip);
0099     return err;
0100 }
0101 
0102 void snd_ak4117_reg_write(struct ak4117 *chip, unsigned char reg, unsigned char mask, unsigned char val)
0103 {
0104     if (reg >= 5)
0105         return;
0106     reg_write(chip, reg, (chip->regmap[reg] & ~mask) | val);
0107 }
0108 
0109 void snd_ak4117_reinit(struct ak4117 *chip)
0110 {
0111     unsigned char old = chip->regmap[AK4117_REG_PWRDN], reg;
0112 
0113     del_timer(&chip->timer);
0114     chip->init = 1;
0115     /* bring the chip to reset state and powerdown state */
0116     reg_write(chip, AK4117_REG_PWRDN, 0);
0117     udelay(200);
0118     /* release reset, but leave powerdown */
0119     reg_write(chip, AK4117_REG_PWRDN, (old | AK4117_RST) & ~AK4117_PWN);
0120     udelay(200);
0121     for (reg = 1; reg < 5; reg++)
0122         reg_write(chip, reg, chip->regmap[reg]);
0123     /* release powerdown, everything is initialized now */
0124     reg_write(chip, AK4117_REG_PWRDN, old | AK4117_RST | AK4117_PWN);
0125     chip->init = 0;
0126     mod_timer(&chip->timer, 1 + jiffies);
0127 }
0128 
0129 static unsigned int external_rate(unsigned char rcs1)
0130 {
0131     switch (rcs1 & (AK4117_FS0|AK4117_FS1|AK4117_FS2|AK4117_FS3)) {
0132     case AK4117_FS_32000HZ: return 32000;
0133     case AK4117_FS_44100HZ: return 44100;
0134     case AK4117_FS_48000HZ: return 48000;
0135     case AK4117_FS_88200HZ: return 88200;
0136     case AK4117_FS_96000HZ: return 96000;
0137     case AK4117_FS_176400HZ: return 176400;
0138     case AK4117_FS_192000HZ: return 192000;
0139     default:        return 0;
0140     }
0141 }
0142 
0143 static int snd_ak4117_in_error_info(struct snd_kcontrol *kcontrol,
0144                     struct snd_ctl_elem_info *uinfo)
0145 {
0146     uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
0147     uinfo->count = 1;
0148     uinfo->value.integer.min = 0;
0149     uinfo->value.integer.max = LONG_MAX;
0150     return 0;
0151 }
0152 
0153 static int snd_ak4117_in_error_get(struct snd_kcontrol *kcontrol,
0154                    struct snd_ctl_elem_value *ucontrol)
0155 {
0156     struct ak4117 *chip = snd_kcontrol_chip(kcontrol);
0157 
0158     spin_lock_irq(&chip->lock);
0159     ucontrol->value.integer.value[0] =
0160                chip->errors[kcontrol->private_value];
0161     chip->errors[kcontrol->private_value] = 0;
0162     spin_unlock_irq(&chip->lock);
0163     return 0;
0164 }
0165 
0166 #define snd_ak4117_in_bit_info      snd_ctl_boolean_mono_info
0167 
0168 static int snd_ak4117_in_bit_get(struct snd_kcontrol *kcontrol,
0169                  struct snd_ctl_elem_value *ucontrol)
0170 {
0171     struct ak4117 *chip = snd_kcontrol_chip(kcontrol);
0172     unsigned char reg = kcontrol->private_value & 0xff;
0173     unsigned char bit = (kcontrol->private_value >> 8) & 0xff;
0174     unsigned char inv = (kcontrol->private_value >> 31) & 1;
0175 
0176     ucontrol->value.integer.value[0] = ((reg_read(chip, reg) & (1 << bit)) ? 1 : 0) ^ inv;
0177     return 0;
0178 }
0179 
0180 static int snd_ak4117_rx_info(struct snd_kcontrol *kcontrol,
0181                   struct snd_ctl_elem_info *uinfo)
0182 {
0183     uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
0184     uinfo->count = 1;
0185     uinfo->value.integer.min = 0;
0186     uinfo->value.integer.max = 1;
0187     return 0;
0188 }
0189 
0190 static int snd_ak4117_rx_get(struct snd_kcontrol *kcontrol,
0191                  struct snd_ctl_elem_value *ucontrol)
0192 {
0193     struct ak4117 *chip = snd_kcontrol_chip(kcontrol);
0194 
0195     ucontrol->value.integer.value[0] = (chip->regmap[AK4117_REG_IO] & AK4117_IPS) ? 1 : 0;
0196     return 0;
0197 }
0198 
0199 static int snd_ak4117_rx_put(struct snd_kcontrol *kcontrol,
0200                  struct snd_ctl_elem_value *ucontrol)
0201 {
0202     struct ak4117 *chip = snd_kcontrol_chip(kcontrol);
0203     int change;
0204     u8 old_val;
0205     
0206     spin_lock_irq(&chip->lock);
0207     old_val = chip->regmap[AK4117_REG_IO];
0208     change = !!ucontrol->value.integer.value[0] != ((old_val & AK4117_IPS) ? 1 : 0);
0209     if (change)
0210         reg_write(chip, AK4117_REG_IO, (old_val & ~AK4117_IPS) | (ucontrol->value.integer.value[0] ? AK4117_IPS : 0));
0211     spin_unlock_irq(&chip->lock);
0212     return change;
0213 }
0214 
0215 static int snd_ak4117_rate_info(struct snd_kcontrol *kcontrol,
0216                 struct snd_ctl_elem_info *uinfo)
0217 {
0218     uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
0219     uinfo->count = 1;
0220     uinfo->value.integer.min = 0;
0221     uinfo->value.integer.max = 192000;
0222     return 0;
0223 }
0224 
0225 static int snd_ak4117_rate_get(struct snd_kcontrol *kcontrol,
0226                    struct snd_ctl_elem_value *ucontrol)
0227 {
0228     struct ak4117 *chip = snd_kcontrol_chip(kcontrol);
0229 
0230     ucontrol->value.integer.value[0] = external_rate(reg_read(chip, AK4117_REG_RCS1));
0231     return 0;
0232 }
0233 
0234 static int snd_ak4117_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
0235 {
0236     uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
0237     uinfo->count = 1;
0238     return 0;
0239 }
0240 
0241 static int snd_ak4117_spdif_get(struct snd_kcontrol *kcontrol,
0242                 struct snd_ctl_elem_value *ucontrol)
0243 {
0244     struct ak4117 *chip = snd_kcontrol_chip(kcontrol);
0245     unsigned i;
0246 
0247     for (i = 0; i < AK4117_REG_RXCSB_SIZE; i++)
0248         ucontrol->value.iec958.status[i] = reg_read(chip, AK4117_REG_RXCSB0 + i);
0249     return 0;
0250 }
0251 
0252 static int snd_ak4117_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
0253 {
0254     uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
0255     uinfo->count = 1;
0256     return 0;
0257 }
0258 
0259 static int snd_ak4117_spdif_mask_get(struct snd_kcontrol *kcontrol,
0260                       struct snd_ctl_elem_value *ucontrol)
0261 {
0262     memset(ucontrol->value.iec958.status, 0xff, AK4117_REG_RXCSB_SIZE);
0263     return 0;
0264 }
0265 
0266 static int snd_ak4117_spdif_pinfo(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
0267 {
0268     uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
0269     uinfo->value.integer.min = 0;
0270     uinfo->value.integer.max = 0xffff;
0271     uinfo->count = 4;
0272     return 0;
0273 }
0274 
0275 static int snd_ak4117_spdif_pget(struct snd_kcontrol *kcontrol,
0276                  struct snd_ctl_elem_value *ucontrol)
0277 {
0278     struct ak4117 *chip = snd_kcontrol_chip(kcontrol);
0279     unsigned short tmp;
0280 
0281     ucontrol->value.integer.value[0] = 0xf8f2;
0282     ucontrol->value.integer.value[1] = 0x4e1f;
0283     tmp = reg_read(chip, AK4117_REG_Pc0) | (reg_read(chip, AK4117_REG_Pc1) << 8);
0284     ucontrol->value.integer.value[2] = tmp;
0285     tmp = reg_read(chip, AK4117_REG_Pd0) | (reg_read(chip, AK4117_REG_Pd1) << 8);
0286     ucontrol->value.integer.value[3] = tmp;
0287     return 0;
0288 }
0289 
0290 static int snd_ak4117_spdif_qinfo(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
0291 {
0292     uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
0293     uinfo->count = AK4117_REG_QSUB_SIZE;
0294     return 0;
0295 }
0296 
0297 static int snd_ak4117_spdif_qget(struct snd_kcontrol *kcontrol,
0298                  struct snd_ctl_elem_value *ucontrol)
0299 {
0300     struct ak4117 *chip = snd_kcontrol_chip(kcontrol);
0301     unsigned i;
0302 
0303     for (i = 0; i < AK4117_REG_QSUB_SIZE; i++)
0304         ucontrol->value.bytes.data[i] = reg_read(chip, AK4117_REG_QSUB_ADDR + i);
0305     return 0;
0306 }
0307 
0308 /* Don't forget to change AK4117_CONTROLS define!!! */
0309 static const struct snd_kcontrol_new snd_ak4117_iec958_controls[] = {
0310 {
0311     .iface =    SNDRV_CTL_ELEM_IFACE_PCM,
0312     .name =     "IEC958 Parity Errors",
0313     .access =   SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
0314     .info =     snd_ak4117_in_error_info,
0315     .get =      snd_ak4117_in_error_get,
0316     .private_value = AK4117_PARITY_ERRORS,
0317 },
0318 {
0319     .iface =    SNDRV_CTL_ELEM_IFACE_PCM,
0320     .name =     "IEC958 V-Bit Errors",
0321     .access =   SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
0322     .info =     snd_ak4117_in_error_info,
0323     .get =      snd_ak4117_in_error_get,
0324     .private_value = AK4117_V_BIT_ERRORS,
0325 },
0326 {
0327     .iface =    SNDRV_CTL_ELEM_IFACE_PCM,
0328     .name =     "IEC958 C-CRC Errors",
0329     .access =   SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
0330     .info =     snd_ak4117_in_error_info,
0331     .get =      snd_ak4117_in_error_get,
0332     .private_value = AK4117_CCRC_ERRORS,
0333 },
0334 {
0335     .iface =    SNDRV_CTL_ELEM_IFACE_PCM,
0336     .name =     "IEC958 Q-CRC Errors",
0337     .access =   SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
0338     .info =     snd_ak4117_in_error_info,
0339     .get =      snd_ak4117_in_error_get,
0340     .private_value = AK4117_QCRC_ERRORS,
0341 },
0342 {
0343     .iface =    SNDRV_CTL_ELEM_IFACE_PCM,
0344     .name =     "IEC958 External Rate",
0345     .access =   SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
0346     .info =     snd_ak4117_rate_info,
0347     .get =      snd_ak4117_rate_get,
0348 },
0349 {
0350     .iface =    SNDRV_CTL_ELEM_IFACE_PCM,
0351     .name =     SNDRV_CTL_NAME_IEC958("",CAPTURE,MASK),
0352     .access =   SNDRV_CTL_ELEM_ACCESS_READ,
0353     .info =     snd_ak4117_spdif_mask_info,
0354     .get =      snd_ak4117_spdif_mask_get,
0355 },
0356 {
0357     .iface =    SNDRV_CTL_ELEM_IFACE_PCM,
0358     .name =     SNDRV_CTL_NAME_IEC958("",CAPTURE,DEFAULT),
0359     .access =   SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
0360     .info =     snd_ak4117_spdif_info,
0361     .get =      snd_ak4117_spdif_get,
0362 },
0363 {
0364     .iface =    SNDRV_CTL_ELEM_IFACE_PCM,
0365     .name =     "IEC958 Preamble Capture Default",
0366     .access =   SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
0367     .info =     snd_ak4117_spdif_pinfo,
0368     .get =      snd_ak4117_spdif_pget,
0369 },
0370 {
0371     .iface =    SNDRV_CTL_ELEM_IFACE_PCM,
0372     .name =     "IEC958 Q-subcode Capture Default",
0373     .access =   SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
0374     .info =     snd_ak4117_spdif_qinfo,
0375     .get =      snd_ak4117_spdif_qget,
0376 },
0377 {
0378     .iface =    SNDRV_CTL_ELEM_IFACE_PCM,
0379     .name =     "IEC958 Audio",
0380     .access =   SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
0381     .info =     snd_ak4117_in_bit_info,
0382     .get =      snd_ak4117_in_bit_get,
0383     .private_value = (1<<31) | (3<<8) | AK4117_REG_RCS0,
0384 },
0385 {
0386     .iface =    SNDRV_CTL_ELEM_IFACE_PCM,
0387     .name =     "IEC958 Non-PCM Bitstream",
0388     .access =   SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
0389     .info =     snd_ak4117_in_bit_info,
0390     .get =      snd_ak4117_in_bit_get,
0391     .private_value = (5<<8) | AK4117_REG_RCS1,
0392 },
0393 {
0394     .iface =    SNDRV_CTL_ELEM_IFACE_PCM,
0395     .name =     "IEC958 DTS Bitstream",
0396     .access =   SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
0397     .info =     snd_ak4117_in_bit_info,
0398     .get =      snd_ak4117_in_bit_get,
0399     .private_value = (6<<8) | AK4117_REG_RCS1,
0400 },
0401 {
0402     .iface =    SNDRV_CTL_ELEM_IFACE_PCM,
0403     .name =     "AK4117 Input Select",
0404     .access =   SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE,
0405     .info =     snd_ak4117_rx_info,
0406     .get =      snd_ak4117_rx_get,
0407     .put =      snd_ak4117_rx_put,
0408 }
0409 };
0410 
0411 int snd_ak4117_build(struct ak4117 *ak4117, struct snd_pcm_substream *cap_substream)
0412 {
0413     struct snd_kcontrol *kctl;
0414     unsigned int idx;
0415     int err;
0416 
0417     if (snd_BUG_ON(!cap_substream))
0418         return -EINVAL;
0419     ak4117->substream = cap_substream;
0420     for (idx = 0; idx < AK4117_CONTROLS; idx++) {
0421         kctl = snd_ctl_new1(&snd_ak4117_iec958_controls[idx], ak4117);
0422         if (kctl == NULL)
0423             return -ENOMEM;
0424         kctl->id.device = cap_substream->pcm->device;
0425         kctl->id.subdevice = cap_substream->number;
0426         err = snd_ctl_add(ak4117->card, kctl);
0427         if (err < 0)
0428             return err;
0429         ak4117->kctls[idx] = kctl;
0430     }
0431     return 0;
0432 }
0433 
0434 int snd_ak4117_external_rate(struct ak4117 *ak4117)
0435 {
0436     unsigned char rcs1;
0437 
0438     rcs1 = reg_read(ak4117, AK4117_REG_RCS1);
0439     return external_rate(rcs1);
0440 }
0441 
0442 int snd_ak4117_check_rate_and_errors(struct ak4117 *ak4117, unsigned int flags)
0443 {
0444     struct snd_pcm_runtime *runtime = ak4117->substream ? ak4117->substream->runtime : NULL;
0445     unsigned long _flags;
0446     int res = 0;
0447     unsigned char rcs0, rcs1, rcs2;
0448     unsigned char c0, c1;
0449 
0450     rcs1 = reg_read(ak4117, AK4117_REG_RCS1);
0451     if (flags & AK4117_CHECK_NO_STAT)
0452         goto __rate;
0453     rcs0 = reg_read(ak4117, AK4117_REG_RCS0);
0454     rcs2 = reg_read(ak4117, AK4117_REG_RCS2);
0455     // printk(KERN_DEBUG "AK IRQ: rcs0 = 0x%x, rcs1 = 0x%x, rcs2 = 0x%x\n", rcs0, rcs1, rcs2);
0456     spin_lock_irqsave(&ak4117->lock, _flags);
0457     if (rcs0 & AK4117_PAR)
0458         ak4117->errors[AK4117_PARITY_ERRORS]++;
0459     if (rcs0 & AK4117_V)
0460         ak4117->errors[AK4117_V_BIT_ERRORS]++;
0461     if (rcs2 & AK4117_CCRC)
0462         ak4117->errors[AK4117_CCRC_ERRORS]++;
0463     if (rcs2 & AK4117_QCRC)
0464         ak4117->errors[AK4117_QCRC_ERRORS]++;
0465     c0 = (ak4117->rcs0 & (AK4117_QINT | AK4117_CINT | AK4117_STC | AK4117_AUDION | AK4117_AUTO | AK4117_UNLCK)) ^
0466                      (rcs0 & (AK4117_QINT | AK4117_CINT | AK4117_STC | AK4117_AUDION | AK4117_AUTO | AK4117_UNLCK));
0467     c1 = (ak4117->rcs1 & (AK4117_DTSCD | AK4117_NPCM | AK4117_PEM | 0x0f)) ^
0468                  (rcs1 & (AK4117_DTSCD | AK4117_NPCM | AK4117_PEM | 0x0f));
0469     ak4117->rcs0 = rcs0 & ~(AK4117_QINT | AK4117_CINT | AK4117_STC);
0470     ak4117->rcs1 = rcs1;
0471     ak4117->rcs2 = rcs2;
0472     spin_unlock_irqrestore(&ak4117->lock, _flags);
0473 
0474     if (rcs0 & AK4117_PAR)
0475         snd_ctl_notify(ak4117->card, SNDRV_CTL_EVENT_MASK_VALUE, &ak4117->kctls[0]->id);
0476     if (rcs0 & AK4117_V)
0477         snd_ctl_notify(ak4117->card, SNDRV_CTL_EVENT_MASK_VALUE, &ak4117->kctls[1]->id);
0478     if (rcs2 & AK4117_CCRC)
0479         snd_ctl_notify(ak4117->card, SNDRV_CTL_EVENT_MASK_VALUE, &ak4117->kctls[2]->id);
0480     if (rcs2 & AK4117_QCRC)
0481         snd_ctl_notify(ak4117->card, SNDRV_CTL_EVENT_MASK_VALUE, &ak4117->kctls[3]->id);
0482 
0483     /* rate change */
0484     if (c1 & 0x0f)
0485         snd_ctl_notify(ak4117->card, SNDRV_CTL_EVENT_MASK_VALUE, &ak4117->kctls[4]->id);
0486 
0487     if ((c1 & AK4117_PEM) | (c0 & AK4117_CINT))
0488         snd_ctl_notify(ak4117->card, SNDRV_CTL_EVENT_MASK_VALUE, &ak4117->kctls[6]->id);
0489     if (c0 & AK4117_QINT)
0490         snd_ctl_notify(ak4117->card, SNDRV_CTL_EVENT_MASK_VALUE, &ak4117->kctls[8]->id);
0491 
0492     if (c0 & AK4117_AUDION)
0493         snd_ctl_notify(ak4117->card, SNDRV_CTL_EVENT_MASK_VALUE, &ak4117->kctls[9]->id);
0494     if (c1 & AK4117_NPCM)
0495         snd_ctl_notify(ak4117->card, SNDRV_CTL_EVENT_MASK_VALUE, &ak4117->kctls[10]->id);
0496     if (c1 & AK4117_DTSCD)
0497         snd_ctl_notify(ak4117->card, SNDRV_CTL_EVENT_MASK_VALUE, &ak4117->kctls[11]->id);
0498         
0499     if (ak4117->change_callback && (c0 | c1) != 0)
0500         ak4117->change_callback(ak4117, c0, c1);
0501 
0502       __rate:
0503     /* compare rate */
0504     res = external_rate(rcs1);
0505     if (!(flags & AK4117_CHECK_NO_RATE) && runtime && runtime->rate != res) {
0506         snd_pcm_stream_lock_irqsave(ak4117->substream, _flags);
0507         if (snd_pcm_running(ak4117->substream)) {
0508             // printk(KERN_DEBUG "rate changed (%i <- %i)\n", runtime->rate, res);
0509             snd_pcm_stop(ak4117->substream, SNDRV_PCM_STATE_DRAINING);
0510             wake_up(&runtime->sleep);
0511             res = 1;
0512         }
0513         snd_pcm_stream_unlock_irqrestore(ak4117->substream, _flags);
0514     }
0515     return res;
0516 }
0517 
0518 static void snd_ak4117_timer(struct timer_list *t)
0519 {
0520     struct ak4117 *chip = from_timer(chip, t, timer);
0521 
0522     if (chip->init)
0523         return;
0524     snd_ak4117_check_rate_and_errors(chip, 0);
0525     mod_timer(&chip->timer, 1 + jiffies);
0526 }
0527 
0528 EXPORT_SYMBOL(snd_ak4117_create);
0529 EXPORT_SYMBOL(snd_ak4117_reg_write);
0530 EXPORT_SYMBOL(snd_ak4117_reinit);
0531 EXPORT_SYMBOL(snd_ak4117_build);
0532 EXPORT_SYMBOL(snd_ak4117_external_rate);
0533 EXPORT_SYMBOL(snd_ak4117_check_rate_and_errors);
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