firewire/fireworks/fireworks_command.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * fireworks_command.c - a part of driver for Fireworks based devices
0004  *
0005  * Copyright (c) 2013-2014 Takashi Sakamoto
0006  */
0007
0008 #include "./fireworks.h"
0009
0010 /*
0011  * This driver uses transaction version 1 or later to use extended hardware
0012  * information. Then too old devices are not available.
0013  *
0014  * Each commands are not required to have continuous sequence numbers. This
0015  * number is just used to match command and response.
0016  *
0017  * This module support a part of commands. Please see FFADO if you want to see
0018  * whole commands. But there are some commands which FFADO don't implement.
0019  *
0020  * Fireworks also supports AV/C general commands and AV/C Stream Format
0021  * Information commands. But this module don't use them.
0022  */
0023
0024 #define KERNEL_SEQNUM_MIN   (SND_EFW_TRANSACTION_USER_SEQNUM_MAX + 2)
0025 #define KERNEL_SEQNUM_MAX   ((u32)~0)
0026
0027 /* for clock source and sampling rate */
0028 struct efc_clock {
0029     u32 source;
0030     u32 sampling_rate;
0031     u32 index;
0032 };
0033
0034 /* command categories */
0035 enum efc_category {
0036     EFC_CAT_HWINFO      = 0,
0037     EFC_CAT_TRANSPORT   = 2,
0038     EFC_CAT_HWCTL       = 3,
0039 };
0040
0041 /* hardware info category commands */
0042 enum efc_cmd_hwinfo {
0043     EFC_CMD_HWINFO_GET_CAPS     = 0,
0044     EFC_CMD_HWINFO_GET_POLLED   = 1,
0045     EFC_CMD_HWINFO_SET_RESP_ADDR    = 2
0046 };
0047
0048 enum efc_cmd_transport {
0049     EFC_CMD_TRANSPORT_SET_TX_MODE   = 0
0050 };
0051
0052 /* hardware control category commands */
0053 enum efc_cmd_hwctl {
0054     EFC_CMD_HWCTL_SET_CLOCK     = 0,
0055     EFC_CMD_HWCTL_GET_CLOCK     = 1,
0056     EFC_CMD_HWCTL_IDENTIFY      = 5
0057 };
0058
0059 /* return values in response */
0060 enum efr_status {
0061     EFR_STATUS_OK           = 0,
0062     EFR_STATUS_BAD          = 1,
0063     EFR_STATUS_BAD_COMMAND      = 2,
0064     EFR_STATUS_COMM_ERR     = 3,
0065     EFR_STATUS_BAD_QUAD_COUNT   = 4,
0066     EFR_STATUS_UNSUPPORTED      = 5,
0067     EFR_STATUS_1394_TIMEOUT     = 6,
0068     EFR_STATUS_DSP_TIMEOUT      = 7,
0069     EFR_STATUS_BAD_RATE     = 8,
0070     EFR_STATUS_BAD_CLOCK        = 9,
0071     EFR_STATUS_BAD_CHANNEL      = 10,
0072     EFR_STATUS_BAD_PAN      = 11,
0073     EFR_STATUS_FLASH_BUSY       = 12,
0074     EFR_STATUS_BAD_MIRROR       = 13,
0075     EFR_STATUS_BAD_LED      = 14,
0076     EFR_STATUS_BAD_PARAMETER    = 15,
0077     EFR_STATUS_INCOMPLETE       = 0x80000000
0078 };
0079
0080 static const char *const efr_status_names[] = {
0081     [EFR_STATUS_OK]         = "OK",
0082     [EFR_STATUS_BAD]        = "bad",
0083     [EFR_STATUS_BAD_COMMAND]    = "bad command",
0084     [EFR_STATUS_COMM_ERR]       = "comm err",
0085     [EFR_STATUS_BAD_QUAD_COUNT] = "bad quad count",
0086     [EFR_STATUS_UNSUPPORTED]    = "unsupported",
0087     [EFR_STATUS_1394_TIMEOUT]   = "1394 timeout",
0088     [EFR_STATUS_DSP_TIMEOUT]    = "DSP timeout",
0089     [EFR_STATUS_BAD_RATE]       = "bad rate",
0090     [EFR_STATUS_BAD_CLOCK]      = "bad clock",
0091     [EFR_STATUS_BAD_CHANNEL]    = "bad channel",
0092     [EFR_STATUS_BAD_PAN]        = "bad pan",
0093     [EFR_STATUS_FLASH_BUSY]     = "flash busy",
0094     [EFR_STATUS_BAD_MIRROR]     = "bad mirror",
0095     [EFR_STATUS_BAD_LED]        = "bad LED",
0096     [EFR_STATUS_BAD_PARAMETER]  = "bad parameter",
0097     [EFR_STATUS_BAD_PARAMETER + 1]  = "incomplete"
0098 };
0099
0100 static int
0101 efw_transaction(struct snd_efw *efw, unsigned int category,
0102         unsigned int command,
0103         const __be32 *params, unsigned int param_bytes,
0104         const __be32 *resp, unsigned int resp_bytes)
0105 {
0106     struct snd_efw_transaction *header;
0107     __be32 *buf;
0108     u32 seqnum;
0109     unsigned int buf_bytes, cmd_bytes;
0110     int err;
0111
0112     /* calculate buffer size*/
0113     buf_bytes = sizeof(struct snd_efw_transaction) +
0114             max(param_bytes, resp_bytes);
0115
0116     /* keep buffer */
0117     buf = kzalloc(buf_bytes, GFP_KERNEL);
0118     if (buf == NULL)
0119         return -ENOMEM;
0120
0121     /* to keep consistency of sequence number */
0122     spin_lock(&efw->lock);
0123     if ((efw->seqnum < KERNEL_SEQNUM_MIN) ||
0124         (efw->seqnum >= KERNEL_SEQNUM_MAX - 2))
0125         efw->seqnum = KERNEL_SEQNUM_MIN;
0126     else
0127         efw->seqnum += 2;
0128     seqnum = efw->seqnum;
0129     spin_unlock(&efw->lock);
0130
0131     /* fill transaction header fields */
0132     cmd_bytes = sizeof(struct snd_efw_transaction) + param_bytes;
0133     header = (struct snd_efw_transaction *)buf;
0134     header->length   = cpu_to_be32(cmd_bytes / sizeof(__be32));
0135     header->version  = cpu_to_be32(1);
0136     header->seqnum   = cpu_to_be32(seqnum);
0137     header->category = cpu_to_be32(category);
0138     header->command  = cpu_to_be32(command);
0139     header->status   = 0;
0140
0141     /* fill transaction command parameters */
0142     memcpy(header->params, params, param_bytes);
0143
0144     err = snd_efw_transaction_run(efw->unit, buf, cmd_bytes,
0145                       buf, buf_bytes);
0146     if (err < 0)
0147         goto end;
0148
0149     /* check transaction header fields */
0150     if ((be32_to_cpu(header->version) < 1) ||
0151         (be32_to_cpu(header->category) != category) ||
0152         (be32_to_cpu(header->command) != command) ||
0153         (be32_to_cpu(header->status) != EFR_STATUS_OK)) {
0154         dev_err(&efw->unit->device, "EFW command failed [%u/%u]: %s\n",
0155             be32_to_cpu(header->category),
0156             be32_to_cpu(header->command),
0157             efr_status_names[be32_to_cpu(header->status)]);
0158         err = -EIO;
0159         goto end;
0160     }
0161
0162     if (resp == NULL)
0163         goto end;
0164
0165     /* fill transaction response parameters */
0166     memset((void *)resp, 0, resp_bytes);
0167     resp_bytes = min_t(unsigned int, resp_bytes,
0168                be32_to_cpu(header->length) * sizeof(__be32) -
0169                 sizeof(struct snd_efw_transaction));
0170     memcpy((void *)resp, &buf[6], resp_bytes);
0171 end:
0172     kfree(buf);
0173     return err;
0174 }
0175
0176 /*
0177  * The address in host system for transaction response is changable when the
0178  * device supports. struct hwinfo.flags includes its flag. The default is
0179  * MEMORY_SPACE_EFW_RESPONSE.
0180  */
0181 int snd_efw_command_set_resp_addr(struct snd_efw *efw,
0182                   u16 addr_high, u32 addr_low)
0183 {
0184     __be32 addr[2];
0185
0186     addr[0] = cpu_to_be32(addr_high);
0187     addr[1] = cpu_to_be32(addr_low);
0188
0189     if (!efw->resp_addr_changable)
0190         return -ENOSYS;
0191
0192     return efw_transaction(efw, EFC_CAT_HWCTL,
0193                    EFC_CMD_HWINFO_SET_RESP_ADDR,
0194                    addr, sizeof(addr), NULL, 0);
0195 }
0196
0197 /*
0198  * This is for timestamp processing. In Windows mode, all 32bit fields of second
0199  * CIP header in AMDTP transmit packet is used for 'presentation timestamp'. In
0200  * 'no data' packet the value of this field is 0x90ffffff.
0201  */
0202 int snd_efw_command_set_tx_mode(struct snd_efw *efw,
0203                 enum snd_efw_transport_mode mode)
0204 {
0205     __be32 param = cpu_to_be32(mode);
0206     return efw_transaction(efw, EFC_CAT_TRANSPORT,
0207                    EFC_CMD_TRANSPORT_SET_TX_MODE,
0208                    &param, sizeof(param), NULL, 0);
0209 }
0210
0211 int snd_efw_command_get_hwinfo(struct snd_efw *efw,
0212                    struct snd_efw_hwinfo *hwinfo)
0213 {
0214     int err;
0215
0216     err  = efw_transaction(efw, EFC_CAT_HWINFO,
0217                    EFC_CMD_HWINFO_GET_CAPS,
0218                    NULL, 0, (__be32 *)hwinfo, sizeof(*hwinfo));
0219     if (err < 0)
0220         goto end;
0221
0222     be32_to_cpus(&hwinfo->flags);
0223     be32_to_cpus(&hwinfo->guid_hi);
0224     be32_to_cpus(&hwinfo->guid_lo);
0225     be32_to_cpus(&hwinfo->type);
0226     be32_to_cpus(&hwinfo->version);
0227     be32_to_cpus(&hwinfo->supported_clocks);
0228     be32_to_cpus(&hwinfo->amdtp_rx_pcm_channels);
0229     be32_to_cpus(&hwinfo->amdtp_tx_pcm_channels);
0230     be32_to_cpus(&hwinfo->phys_out);
0231     be32_to_cpus(&hwinfo->phys_in);
0232     be32_to_cpus(&hwinfo->phys_out_grp_count);
0233     be32_to_cpus(&hwinfo->phys_in_grp_count);
0234     be32_to_cpus(&hwinfo->midi_out_ports);
0235     be32_to_cpus(&hwinfo->midi_in_ports);
0236     be32_to_cpus(&hwinfo->max_sample_rate);
0237     be32_to_cpus(&hwinfo->min_sample_rate);
0238     be32_to_cpus(&hwinfo->dsp_version);
0239     be32_to_cpus(&hwinfo->arm_version);
0240     be32_to_cpus(&hwinfo->mixer_playback_channels);
0241     be32_to_cpus(&hwinfo->mixer_capture_channels);
0242     be32_to_cpus(&hwinfo->fpga_version);
0243     be32_to_cpus(&hwinfo->amdtp_rx_pcm_channels_2x);
0244     be32_to_cpus(&hwinfo->amdtp_tx_pcm_channels_2x);
0245     be32_to_cpus(&hwinfo->amdtp_rx_pcm_channels_4x);
0246     be32_to_cpus(&hwinfo->amdtp_tx_pcm_channels_4x);
0247
0248     /* ensure terminated */
0249     hwinfo->vendor_name[HWINFO_NAME_SIZE_BYTES - 1] = '\0';
0250     hwinfo->model_name[HWINFO_NAME_SIZE_BYTES  - 1] = '\0';
0251 end:
0252     return err;
0253 }
0254
0255 int snd_efw_command_get_phys_meters(struct snd_efw *efw,
0256                     struct snd_efw_phys_meters *meters,
0257                     unsigned int len)
0258 {
0259     u32 *buf = (u32 *)meters;
0260     unsigned int i;
0261     int err;
0262
0263     err = efw_transaction(efw, EFC_CAT_HWINFO,
0264                   EFC_CMD_HWINFO_GET_POLLED,
0265                   NULL, 0, (__be32 *)meters, len);
0266     if (err >= 0)
0267         for (i = 0; i < len / sizeof(u32); i++)
0268             be32_to_cpus(&buf[i]);
0269
0270     return err;
0271 }
0272
0273 static int
0274 command_get_clock(struct snd_efw *efw, struct efc_clock *clock)
0275 {
0276     int err;
0277
0278     err = efw_transaction(efw, EFC_CAT_HWCTL,
0279                   EFC_CMD_HWCTL_GET_CLOCK,
0280                   NULL, 0,
0281                   (__be32 *)clock, sizeof(struct efc_clock));
0282     if (err >= 0) {
0283         be32_to_cpus(&clock->source);
0284         be32_to_cpus(&clock->sampling_rate);
0285         be32_to_cpus(&clock->index);
0286     }
0287
0288     return err;
0289 }
0290
0291 /* give UINT_MAX if set nothing */
0292 static int
0293 command_set_clock(struct snd_efw *efw,
0294           unsigned int source, unsigned int rate)
0295 {
0296     struct efc_clock clock = {0};
0297     int err;
0298
0299     /* check arguments */
0300     if ((source == UINT_MAX) && (rate == UINT_MAX)) {
0301         err = -EINVAL;
0302         goto end;
0303     }
0304
0305     /* get current status */
0306     err = command_get_clock(efw, &clock);
0307     if (err < 0)
0308         goto end;
0309
0310     /* no need */
0311     if ((clock.source == source) && (clock.sampling_rate == rate))
0312         goto end;
0313
0314     /* set params */
0315     if ((source != UINT_MAX) && (clock.source != source))
0316         clock.source = source;
0317     if ((rate != UINT_MAX) && (clock.sampling_rate != rate))
0318         clock.sampling_rate = rate;
0319     clock.index = 0;
0320
0321     cpu_to_be32s(&clock.source);
0322     cpu_to_be32s(&clock.sampling_rate);
0323     cpu_to_be32s(&clock.index);
0324
0325     err = efw_transaction(efw, EFC_CAT_HWCTL,
0326                   EFC_CMD_HWCTL_SET_CLOCK,
0327                   (__be32 *)&clock, sizeof(struct efc_clock),
0328                   NULL, 0);
0329     if (err < 0)
0330         goto end;
0331
0332     /*
0333      * With firmware version 5.8, just after changing clock state, these
0334      * parameters are not immediately retrieved by get command. In my
0335      * trial, there needs to be 100msec to get changed parameters.
0336      */
0337     msleep(150);
0338 end:
0339     return err;
0340 }
0341
0342 int snd_efw_command_get_clock_source(struct snd_efw *efw,
0343                      enum snd_efw_clock_source *source)
0344 {
0345     int err;
0346     struct efc_clock clock = {0};
0347
0348     err = command_get_clock(efw, &clock);
0349     if (err >= 0)
0350         *source = clock.source;
0351
0352     return err;
0353 }
0354
0355 int snd_efw_command_get_sampling_rate(struct snd_efw *efw, unsigned int *rate)
0356 {
0357     int err;
0358     struct efc_clock clock = {0};
0359
0360     err = command_get_clock(efw, &clock);
0361     if (err >= 0)
0362         *rate = clock.sampling_rate;
0363
0364     return err;
0365 }
0366
0367 int snd_efw_command_set_sampling_rate(struct snd_efw *efw, unsigned int rate)
0368 {
0369     return command_set_clock(efw, UINT_MAX, rate);
0370 }
0371