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0001 // SPDX-License-Identifier: GPL-2.0
0002 // ff-protocol-former.c - a part of driver for RME Fireface series
0003 //
0004 // Copyright (c) 2019 Takashi Sakamoto
0005 //
0006 // Licensed under the terms of the GNU General Public License, version 2.
0007 
0008 #include <linux/delay.h>
0009 
0010 #include "ff.h"
0011 
0012 #define FORMER_REG_SYNC_STATUS      0x0000801c0000ull
0013 /* For block write request. */
0014 #define FORMER_REG_FETCH_PCM_FRAMES 0x0000801c0000ull
0015 #define FORMER_REG_CLOCK_CONFIG     0x0000801c0004ull
0016 
0017 static int parse_clock_bits(u32 data, unsigned int *rate,
0018                 enum snd_ff_clock_src *src)
0019 {
0020     static const struct {
0021         unsigned int rate;
0022         u32 mask;
0023     } *rate_entry, rate_entries[] = {
0024         {  32000, 0x00000002, },
0025         {  44100, 0x00000000, },
0026         {  48000, 0x00000006, },
0027         {  64000, 0x0000000a, },
0028         {  88200, 0x00000008, },
0029         {  96000, 0x0000000e, },
0030         { 128000, 0x00000012, },
0031         { 176400, 0x00000010, },
0032         { 192000, 0x00000016, },
0033     };
0034     static const struct {
0035         enum snd_ff_clock_src src;
0036         u32 mask;
0037     } *clk_entry, clk_entries[] = {
0038         { SND_FF_CLOCK_SRC_ADAT1,   0x00000000, },
0039         { SND_FF_CLOCK_SRC_ADAT2,   0x00000400, },
0040         { SND_FF_CLOCK_SRC_SPDIF,   0x00000c00, },
0041         { SND_FF_CLOCK_SRC_WORD,    0x00001000, },
0042         { SND_FF_CLOCK_SRC_LTC,     0x00001800, },
0043     };
0044     int i;
0045 
0046     for (i = 0; i < ARRAY_SIZE(rate_entries); ++i) {
0047         rate_entry = rate_entries + i;
0048         if ((data & 0x0000001e) == rate_entry->mask) {
0049             *rate = rate_entry->rate;
0050             break;
0051         }
0052     }
0053     if (i == ARRAY_SIZE(rate_entries))
0054         return -EIO;
0055 
0056     if (data & 0x00000001) {
0057         *src = SND_FF_CLOCK_SRC_INTERNAL;
0058     } else {
0059         for (i = 0; i < ARRAY_SIZE(clk_entries); ++i) {
0060             clk_entry = clk_entries + i;
0061             if ((data & 0x00001c00) == clk_entry->mask) {
0062                 *src = clk_entry->src;
0063                 break;
0064             }
0065         }
0066         if (i == ARRAY_SIZE(clk_entries))
0067             return -EIO;
0068     }
0069 
0070     return 0;
0071 }
0072 
0073 static int former_get_clock(struct snd_ff *ff, unsigned int *rate,
0074                 enum snd_ff_clock_src *src)
0075 {
0076     __le32 reg;
0077     u32 data;
0078     int err;
0079 
0080     err = snd_fw_transaction(ff->unit, TCODE_READ_QUADLET_REQUEST,
0081                  FORMER_REG_CLOCK_CONFIG, &reg, sizeof(reg), 0);
0082     if (err < 0)
0083         return err;
0084     data = le32_to_cpu(reg);
0085 
0086     return parse_clock_bits(data, rate, src);
0087 }
0088 
0089 static int former_switch_fetching_mode(struct snd_ff *ff, bool enable)
0090 {
0091     unsigned int count;
0092     __le32 *reg;
0093     int i;
0094     int err;
0095 
0096     count = 0;
0097     for (i = 0; i < SND_FF_STREAM_MODE_COUNT; ++i)
0098         count = max(count, ff->spec->pcm_playback_channels[i]);
0099 
0100     reg = kcalloc(count, sizeof(__le32), GFP_KERNEL);
0101     if (!reg)
0102         return -ENOMEM;
0103 
0104     if (!enable) {
0105         /*
0106          * Each quadlet is corresponding to data channels in a data
0107          * blocks in reverse order. Precisely, quadlets for available
0108          * data channels should be enabled. Here, I take second best
0109          * to fetch PCM frames from all of data channels regardless of
0110          * stf.
0111          */
0112         for (i = 0; i < count; ++i)
0113             reg[i] = cpu_to_le32(0x00000001);
0114     }
0115 
0116     err = snd_fw_transaction(ff->unit, TCODE_WRITE_BLOCK_REQUEST,
0117                  FORMER_REG_FETCH_PCM_FRAMES, reg,
0118                  sizeof(__le32) * count, 0);
0119     kfree(reg);
0120     return err;
0121 }
0122 
0123 static void dump_clock_config(struct snd_ff *ff, struct snd_info_buffer *buffer)
0124 {
0125     __le32 reg;
0126     u32 data;
0127     unsigned int rate;
0128     enum snd_ff_clock_src src;
0129     const char *label;
0130     int err;
0131 
0132     err = snd_fw_transaction(ff->unit, TCODE_READ_BLOCK_REQUEST,
0133                  FORMER_REG_CLOCK_CONFIG, &reg, sizeof(reg), 0);
0134     if (err < 0)
0135         return;
0136     data = le32_to_cpu(reg);
0137 
0138     snd_iprintf(buffer, "Output S/PDIF format: %s (Emphasis: %s)\n",
0139             (data & 0x00000020) ? "Professional" : "Consumer",
0140             (data & 0x00000040) ? "on" : "off");
0141 
0142     snd_iprintf(buffer, "Optical output interface format: %s\n",
0143             (data & 0x00000100) ? "S/PDIF" : "ADAT");
0144 
0145     snd_iprintf(buffer, "Word output single speed: %s\n",
0146             (data & 0x00002000) ? "on" : "off");
0147 
0148     snd_iprintf(buffer, "S/PDIF input interface: %s\n",
0149             (data & 0x00000200) ? "Optical" : "Coaxial");
0150 
0151     err = parse_clock_bits(data, &rate, &src);
0152     if (err < 0)
0153         return;
0154     label = snd_ff_proc_get_clk_label(src);
0155     if (!label)
0156         return;
0157 
0158     snd_iprintf(buffer, "Clock configuration: %d %s\n", rate, label);
0159 }
0160 
0161 static void dump_sync_status(struct snd_ff *ff, struct snd_info_buffer *buffer)
0162 {
0163     static const struct {
0164         char *const label;
0165         u32 locked_mask;
0166         u32 synced_mask;
0167     } *clk_entry, clk_entries[] = {
0168         { "WDClk",  0x40000000, 0x20000000, },
0169         { "S/PDIF", 0x00080000, 0x00040000, },
0170         { "ADAT1",  0x00000400, 0x00001000, },
0171         { "ADAT2",  0x00000800, 0x00002000, },
0172     };
0173     static const struct {
0174         char *const label;
0175         u32 mask;
0176     } *referred_entry, referred_entries[] = {
0177         { "ADAT1",  0x00000000, },
0178         { "ADAT2",  0x00400000, },
0179         { "S/PDIF", 0x00c00000, },
0180         { "WDclk",  0x01000000, },
0181         { "TCO",    0x01400000, },
0182     };
0183     static const struct {
0184         unsigned int rate;
0185         u32 mask;
0186     } *rate_entry, rate_entries[] = {
0187         { 32000,    0x02000000, },
0188         { 44100,    0x04000000, },
0189         { 48000,    0x06000000, },
0190         { 64000,    0x08000000, },
0191         { 88200,    0x0a000000, },
0192         { 96000,    0x0c000000, },
0193         { 128000,   0x0e000000, },
0194         { 176400,   0x10000000, },
0195         { 192000,   0x12000000, },
0196     };
0197     __le32 reg[2];
0198     u32 data[2];
0199     int i;
0200     int err;
0201 
0202     err = snd_fw_transaction(ff->unit, TCODE_READ_BLOCK_REQUEST,
0203                  FORMER_REG_SYNC_STATUS, reg, sizeof(reg), 0);
0204     if (err < 0)
0205         return;
0206     data[0] = le32_to_cpu(reg[0]);
0207     data[1] = le32_to_cpu(reg[1]);
0208 
0209     snd_iprintf(buffer, "External source detection:\n");
0210 
0211     for (i = 0; i < ARRAY_SIZE(clk_entries); ++i) {
0212         const char *state;
0213 
0214         clk_entry = clk_entries + i;
0215         if (data[0] & clk_entry->locked_mask) {
0216             if (data[0] & clk_entry->synced_mask)
0217                 state = "sync";
0218             else
0219                 state = "lock";
0220         } else {
0221             state = "none";
0222         }
0223 
0224         snd_iprintf(buffer, "%s: %s\n", clk_entry->label, state);
0225     }
0226 
0227     snd_iprintf(buffer, "Referred clock:\n");
0228 
0229     if (data[1] & 0x00000001) {
0230         snd_iprintf(buffer, "Internal\n");
0231     } else {
0232         unsigned int rate;
0233         const char *label;
0234 
0235         for (i = 0; i < ARRAY_SIZE(referred_entries); ++i) {
0236             referred_entry = referred_entries + i;
0237             if ((data[0] & 0x1e0000) == referred_entry->mask) {
0238                 label = referred_entry->label;
0239                 break;
0240             }
0241         }
0242         if (i == ARRAY_SIZE(referred_entries))
0243             label = "none";
0244 
0245         for (i = 0; i < ARRAY_SIZE(rate_entries); ++i) {
0246             rate_entry = rate_entries + i;
0247             if ((data[0] & 0x1e000000) == rate_entry->mask) {
0248                 rate = rate_entry->rate;
0249                 break;
0250             }
0251         }
0252         if (i == ARRAY_SIZE(rate_entries))
0253             rate = 0;
0254 
0255         snd_iprintf(buffer, "%s %d\n", label, rate);
0256     }
0257 }
0258 
0259 static void former_dump_status(struct snd_ff *ff,
0260                    struct snd_info_buffer *buffer)
0261 {
0262     dump_clock_config(ff, buffer);
0263     dump_sync_status(ff, buffer);
0264 }
0265 
0266 static int former_fill_midi_msg(struct snd_ff *ff,
0267                 struct snd_rawmidi_substream *substream,
0268                 unsigned int port)
0269 {
0270     u8 *buf = (u8 *)ff->msg_buf[port];
0271     int len;
0272     int i;
0273 
0274     len = snd_rawmidi_transmit_peek(substream, buf,
0275                     SND_FF_MAXIMIM_MIDI_QUADS);
0276     if (len <= 0)
0277         return len;
0278 
0279     // One quadlet includes one byte.
0280     for (i = len - 1; i >= 0; --i)
0281         ff->msg_buf[port][i] = cpu_to_le32(buf[i]);
0282     ff->rx_bytes[port] = len;
0283 
0284     return len;
0285 }
0286 
0287 #define FF800_STF       0x0000fc88f000
0288 #define FF800_RX_PACKET_FORMAT  0x0000fc88f004
0289 #define FF800_ALLOC_TX_STREAM   0x0000fc88f008
0290 #define FF800_ISOC_COMM_START   0x0000fc88f00c
0291 #define   FF800_TX_S800_FLAG    0x00000800
0292 #define FF800_ISOC_COMM_STOP    0x0000fc88f010
0293 
0294 #define FF800_TX_PACKET_ISOC_CH 0x0000801c0008
0295 
0296 static int allocate_tx_resources(struct snd_ff *ff)
0297 {
0298     __le32 reg;
0299     unsigned int count;
0300     unsigned int tx_isoc_channel;
0301     int err;
0302 
0303     reg = cpu_to_le32(ff->tx_stream.data_block_quadlets);
0304     err = snd_fw_transaction(ff->unit, TCODE_WRITE_QUADLET_REQUEST,
0305                  FF800_ALLOC_TX_STREAM, &reg, sizeof(reg), 0);
0306     if (err < 0)
0307         return err;
0308 
0309     // Wait till the format of tx packet is available.
0310     count = 0;
0311     while (count++ < 10) {
0312         u32 data;
0313         err = snd_fw_transaction(ff->unit, TCODE_READ_QUADLET_REQUEST,
0314                 FF800_TX_PACKET_ISOC_CH, &reg, sizeof(reg), 0);
0315         if (err < 0)
0316             return err;
0317 
0318         data = le32_to_cpu(reg);
0319         if (data != 0xffffffff) {
0320             tx_isoc_channel = data;
0321             break;
0322         }
0323 
0324         msleep(50);
0325     }
0326     if (count >= 10)
0327         return -ETIMEDOUT;
0328 
0329     // NOTE: this is a makeshift to start OHCI 1394 IR context in the
0330     // channel. On the other hand, 'struct fw_iso_resources.allocated' is
0331     // not true and it's not deallocated at stop.
0332     ff->tx_resources.channel = tx_isoc_channel;
0333 
0334     return 0;
0335 }
0336 
0337 static int ff800_allocate_resources(struct snd_ff *ff, unsigned int rate)
0338 {
0339     u32 data;
0340     __le32 reg;
0341     int err;
0342 
0343     reg = cpu_to_le32(rate);
0344     err = snd_fw_transaction(ff->unit, TCODE_WRITE_QUADLET_REQUEST,
0345                  FF800_STF, &reg, sizeof(reg), 0);
0346     if (err < 0)
0347         return err;
0348 
0349     // If starting isochronous communication immediately, change of STF has
0350     // no effect. In this case, the communication runs based on former STF.
0351     // Let's sleep for a bit.
0352     msleep(100);
0353 
0354     // Controllers should allocate isochronous resources for rx stream.
0355     err = fw_iso_resources_allocate(&ff->rx_resources,
0356                 amdtp_stream_get_max_payload(&ff->rx_stream),
0357                 fw_parent_device(ff->unit)->max_speed);
0358     if (err < 0)
0359         return err;
0360 
0361     // Set isochronous channel and the number of quadlets of rx packets.
0362     // This should be done before the allocation of tx resources to avoid
0363     // periodical noise.
0364     data = ff->rx_stream.data_block_quadlets << 3;
0365     data = (data << 8) | ff->rx_resources.channel;
0366     reg = cpu_to_le32(data);
0367     err = snd_fw_transaction(ff->unit, TCODE_WRITE_QUADLET_REQUEST,
0368                  FF800_RX_PACKET_FORMAT, &reg, sizeof(reg), 0);
0369     if (err < 0)
0370         return err;
0371 
0372     return allocate_tx_resources(ff);
0373 }
0374 
0375 static int ff800_begin_session(struct snd_ff *ff, unsigned int rate)
0376 {
0377     unsigned int generation = ff->rx_resources.generation;
0378     __le32 reg;
0379 
0380     if (generation != fw_parent_device(ff->unit)->card->generation) {
0381         int err = fw_iso_resources_update(&ff->rx_resources);
0382         if (err < 0)
0383             return err;
0384     }
0385 
0386     reg = cpu_to_le32(0x80000000);
0387     reg |= cpu_to_le32(ff->tx_stream.data_block_quadlets);
0388     if (fw_parent_device(ff->unit)->max_speed == SCODE_800)
0389         reg |= cpu_to_le32(FF800_TX_S800_FLAG);
0390     return snd_fw_transaction(ff->unit, TCODE_WRITE_QUADLET_REQUEST,
0391                  FF800_ISOC_COMM_START, &reg, sizeof(reg), 0);
0392 }
0393 
0394 static void ff800_finish_session(struct snd_ff *ff)
0395 {
0396     __le32 reg;
0397 
0398     reg = cpu_to_le32(0x80000000);
0399     snd_fw_transaction(ff->unit, TCODE_WRITE_QUADLET_REQUEST,
0400                FF800_ISOC_COMM_STOP, &reg, sizeof(reg), 0);
0401 }
0402 
0403 // Fireface 800 doesn't allow drivers to register lower 4 bytes of destination
0404 // address.
0405 // A write transaction to clear registered higher 4 bytes of destination address
0406 // has an effect to suppress asynchronous transaction from device.
0407 static void ff800_handle_midi_msg(struct snd_ff *ff, unsigned int offset,
0408                   __le32 *buf, size_t length)
0409 {
0410     int i;
0411 
0412     for (i = 0; i < length / 4; i++) {
0413         u8 byte = le32_to_cpu(buf[i]) & 0xff;
0414         struct snd_rawmidi_substream *substream;
0415 
0416         substream = READ_ONCE(ff->tx_midi_substreams[0]);
0417         if (substream)
0418             snd_rawmidi_receive(substream, &byte, 1);
0419     }
0420 }
0421 
0422 const struct snd_ff_protocol snd_ff_protocol_ff800 = {
0423     .handle_midi_msg    = ff800_handle_midi_msg,
0424     .fill_midi_msg      = former_fill_midi_msg,
0425     .get_clock      = former_get_clock,
0426     .switch_fetching_mode   = former_switch_fetching_mode,
0427     .allocate_resources = ff800_allocate_resources,
0428     .begin_session      = ff800_begin_session,
0429     .finish_session     = ff800_finish_session,
0430     .dump_status        = former_dump_status,
0431 };
0432 
0433 #define FF400_STF       0x000080100500ull
0434 #define FF400_RX_PACKET_FORMAT  0x000080100504ull
0435 #define FF400_ISOC_COMM_START   0x000080100508ull
0436 #define FF400_TX_PACKET_FORMAT  0x00008010050cull
0437 #define FF400_ISOC_COMM_STOP    0x000080100510ull
0438 
0439 // Fireface 400 manages isochronous channel number in 3 bit field. Therefore,
0440 // we can allocate between 0 and 7 channel.
0441 static int ff400_allocate_resources(struct snd_ff *ff, unsigned int rate)
0442 {
0443     __le32 reg;
0444     enum snd_ff_stream_mode mode;
0445     int i;
0446     int err;
0447 
0448     // Check whether the given value is supported or not.
0449     for (i = 0; i < CIP_SFC_COUNT; i++) {
0450         if (amdtp_rate_table[i] == rate)
0451             break;
0452     }
0453     if (i >= CIP_SFC_COUNT)
0454         return -EINVAL;
0455 
0456     // Set the number of data blocks transferred in a second.
0457     reg = cpu_to_le32(rate);
0458     err = snd_fw_transaction(ff->unit, TCODE_WRITE_QUADLET_REQUEST,
0459                  FF400_STF, &reg, sizeof(reg), 0);
0460     if (err < 0)
0461         return err;
0462 
0463     msleep(100);
0464 
0465     err = snd_ff_stream_get_multiplier_mode(i, &mode);
0466     if (err < 0)
0467         return err;
0468 
0469     // Keep resources for in-stream.
0470     ff->tx_resources.channels_mask = 0x00000000000000ffuLL;
0471     err = fw_iso_resources_allocate(&ff->tx_resources,
0472             amdtp_stream_get_max_payload(&ff->tx_stream),
0473             fw_parent_device(ff->unit)->max_speed);
0474     if (err < 0)
0475         return err;
0476 
0477     // Keep resources for out-stream.
0478     ff->rx_resources.channels_mask = 0x00000000000000ffuLL;
0479     err = fw_iso_resources_allocate(&ff->rx_resources,
0480             amdtp_stream_get_max_payload(&ff->rx_stream),
0481             fw_parent_device(ff->unit)->max_speed);
0482     if (err < 0)
0483         fw_iso_resources_free(&ff->tx_resources);
0484 
0485     return err;
0486 }
0487 
0488 static int ff400_begin_session(struct snd_ff *ff, unsigned int rate)
0489 {
0490     unsigned int generation = ff->rx_resources.generation;
0491     __le32 reg;
0492     int err;
0493 
0494     if (generation != fw_parent_device(ff->unit)->card->generation) {
0495         err = fw_iso_resources_update(&ff->tx_resources);
0496         if (err < 0)
0497             return err;
0498 
0499         err = fw_iso_resources_update(&ff->rx_resources);
0500         if (err < 0)
0501             return err;
0502     }
0503 
0504     // Set isochronous channel and the number of quadlets of received
0505     // packets.
0506     reg = cpu_to_le32(((ff->rx_stream.data_block_quadlets << 3) << 8) |
0507               ff->rx_resources.channel);
0508     err = snd_fw_transaction(ff->unit, TCODE_WRITE_QUADLET_REQUEST,
0509                  FF400_RX_PACKET_FORMAT, &reg, sizeof(reg), 0);
0510     if (err < 0)
0511         return err;
0512 
0513     // Set isochronous channel and the number of quadlets of transmitted
0514     // packet.
0515     // TODO: investigate the purpose of this 0x80.
0516     reg = cpu_to_le32((0x80 << 24) |
0517               (ff->tx_resources.channel << 5) |
0518               (ff->tx_stream.data_block_quadlets));
0519     err = snd_fw_transaction(ff->unit, TCODE_WRITE_QUADLET_REQUEST,
0520                  FF400_TX_PACKET_FORMAT, &reg, sizeof(reg), 0);
0521     if (err < 0)
0522         return err;
0523 
0524     // Allow to transmit packets.
0525     reg = cpu_to_le32(0x00000001);
0526     return snd_fw_transaction(ff->unit, TCODE_WRITE_QUADLET_REQUEST,
0527                  FF400_ISOC_COMM_START, &reg, sizeof(reg), 0);
0528 }
0529 
0530 static void ff400_finish_session(struct snd_ff *ff)
0531 {
0532     __le32 reg;
0533 
0534     reg = cpu_to_le32(0x80000000);
0535     snd_fw_transaction(ff->unit, TCODE_WRITE_QUADLET_REQUEST,
0536                FF400_ISOC_COMM_STOP, &reg, sizeof(reg), 0);
0537 }
0538 
0539 // For Fireface 400, lower 4 bytes of destination address is configured by bit
0540 // flag in quadlet register (little endian) at 0x'0000'801'0051c. Drivers can
0541 // select one of 4 options:
0542 //
0543 // bit flags: offset of destination address
0544 //  - 0x04000000: 0x'....'....'0000'0000
0545 //  - 0x08000000: 0x'....'....'0000'0080
0546 //  - 0x10000000: 0x'....'....'0000'0100
0547 //  - 0x20000000: 0x'....'....'0000'0180
0548 //
0549 // Drivers can suppress the device to transfer asynchronous transactions by
0550 // using below 2 bits.
0551 //  - 0x01000000: suppress transmission
0552 //  - 0x02000000: suppress transmission
0553 //
0554 // Actually, the register is write-only and includes the other options such as
0555 // input attenuation. This driver allocates destination address with '0000'0000
0556 // in its lower offset and expects userspace application to configure the
0557 // register for it.
0558 static void ff400_handle_midi_msg(struct snd_ff *ff, unsigned int offset,
0559                   __le32 *buf, size_t length)
0560 {
0561     int i;
0562 
0563     for (i = 0; i < length / 4; i++) {
0564         u32 quad = le32_to_cpu(buf[i]);
0565         u8 byte;
0566         unsigned int index;
0567         struct snd_rawmidi_substream *substream;
0568 
0569         /* Message in first port. */
0570         /*
0571          * This value may represent the index of this unit when the same
0572          * units are on the same IEEE 1394 bus. This driver doesn't use
0573          * it.
0574          */
0575         index = (quad >> 8) & 0xff;
0576         if (index > 0) {
0577             substream = READ_ONCE(ff->tx_midi_substreams[0]);
0578             if (substream != NULL) {
0579                 byte = quad & 0xff;
0580                 snd_rawmidi_receive(substream, &byte, 1);
0581             }
0582         }
0583 
0584         /* Message in second port. */
0585         index = (quad >> 24) & 0xff;
0586         if (index > 0) {
0587             substream = READ_ONCE(ff->tx_midi_substreams[1]);
0588             if (substream != NULL) {
0589                 byte = (quad >> 16) & 0xff;
0590                 snd_rawmidi_receive(substream, &byte, 1);
0591             }
0592         }
0593     }
0594 }
0595 
0596 const struct snd_ff_protocol snd_ff_protocol_ff400 = {
0597     .handle_midi_msg    = ff400_handle_midi_msg,
0598     .fill_midi_msg      = former_fill_midi_msg,
0599     .get_clock      = former_get_clock,
0600     .switch_fetching_mode   = former_switch_fetching_mode,
0601     .allocate_resources = ff400_allocate_resources,
0602     .begin_session      = ff400_begin_session,
0603     .finish_session     = ff400_finish_session,
0604     .dump_status        = former_dump_status,
0605 };
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