firewire/digi00x/digi00x.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * digi00x.h - a part of driver for Digidesign Digi 002/003 family
0004  *
0005  * Copyright (c) 2014-2015 Takashi Sakamoto
0006  */
0007
0008 #ifndef SOUND_DIGI00X_H_INCLUDED
0009 #define SOUND_DIGI00X_H_INCLUDED
0010
0011 #include <linux/compat.h>
0012 #include <linux/device.h>
0013 #include <linux/firewire.h>
0014 #include <linux/module.h>
0015 #include <linux/mod_devicetable.h>
0016 #include <linux/delay.h>
0017 #include <linux/slab.h>
0018 #include <linux/sched/signal.h>
0019
0020 #include <sound/core.h>
0021 #include <sound/initval.h>
0022 #include <sound/info.h>
0023 #include <sound/pcm.h>
0024 #include <sound/pcm_params.h>
0025 #include <sound/firewire.h>
0026 #include <sound/hwdep.h>
0027 #include <sound/rawmidi.h>
0028
0029 #include "../lib.h"
0030 #include "../iso-resources.h"
0031 #include "../amdtp-stream.h"
0032
0033 struct snd_dg00x {
0034     struct snd_card *card;
0035     struct fw_unit *unit;
0036
0037     struct mutex mutex;
0038     spinlock_t lock;
0039
0040     struct amdtp_stream tx_stream;
0041     struct fw_iso_resources tx_resources;
0042
0043     struct amdtp_stream rx_stream;
0044     struct fw_iso_resources rx_resources;
0045
0046     unsigned int substreams_counter;
0047
0048     /* for uapi */
0049     int dev_lock_count;
0050     bool dev_lock_changed;
0051     wait_queue_head_t hwdep_wait;
0052
0053     /* For asynchronous messages. */
0054     struct fw_address_handler async_handler;
0055     u32 msg;
0056
0057     /* Console models have additional MIDI ports for control surface. */
0058     bool is_console;
0059
0060     struct amdtp_domain domain;
0061 };
0062
0063 #define DG00X_ADDR_BASE     0xffffe0000000ull
0064
0065 #define DG00X_OFFSET_STREAMING_STATE    0x0000
0066 #define DG00X_OFFSET_STREAMING_SET  0x0004
0067 /* unknown but address in host space    0x0008 */
0068 /* For LSB of the address       0x000c */
0069 /* unknown              0x0010 */
0070 #define DG00X_OFFSET_MESSAGE_ADDR   0x0014
0071 /* For LSB of the address       0x0018 */
0072 /* unknown              0x001c */
0073 /* unknown              0x0020 */
0074 /* not used         0x0024--0x00ff */
0075 #define DG00X_OFFSET_ISOC_CHANNELS  0x0100
0076 /* unknown              0x0104 */
0077 /* unknown              0x0108 */
0078 /* unknown              0x010c */
0079 #define DG00X_OFFSET_LOCAL_RATE     0x0110
0080 #define DG00X_OFFSET_EXTERNAL_RATE  0x0114
0081 #define DG00X_OFFSET_CLOCK_SOURCE   0x0118
0082 #define DG00X_OFFSET_OPT_IFACE_MODE 0x011c
0083 /* unknown              0x0120 */
0084 /* Mixer control on/off         0x0124 */
0085 /* unknown              0x0128 */
0086 #define DG00X_OFFSET_DETECT_EXTERNAL    0x012c
0087 /* unknown              0x0138 */
0088 #define DG00X_OFFSET_MMC        0x0400
0089
0090 enum snd_dg00x_rate {
0091     SND_DG00X_RATE_44100 = 0,
0092     SND_DG00X_RATE_48000,
0093     SND_DG00X_RATE_88200,
0094     SND_DG00X_RATE_96000,
0095     SND_DG00X_RATE_COUNT,
0096 };
0097
0098 enum snd_dg00x_clock {
0099     SND_DG00X_CLOCK_INTERNAL = 0,
0100     SND_DG00X_CLOCK_SPDIF,
0101     SND_DG00X_CLOCK_ADAT,
0102     SND_DG00X_CLOCK_WORD,
0103     SND_DG00X_CLOCK_COUNT,
0104 };
0105
0106 enum snd_dg00x_optical_mode {
0107     SND_DG00X_OPT_IFACE_MODE_ADAT = 0,
0108     SND_DG00X_OPT_IFACE_MODE_SPDIF,
0109     SND_DG00X_OPT_IFACE_MODE_COUNT,
0110 };
0111
0112 #define DOT_MIDI_IN_PORTS   1
0113 #define DOT_MIDI_OUT_PORTS  2
0114
0115 int amdtp_dot_init(struct amdtp_stream *s, struct fw_unit *unit,
0116            enum amdtp_stream_direction dir);
0117 int amdtp_dot_set_parameters(struct amdtp_stream *s, unsigned int rate,
0118                  unsigned int pcm_channels);
0119 void amdtp_dot_reset(struct amdtp_stream *s);
0120 int amdtp_dot_add_pcm_hw_constraints(struct amdtp_stream *s,
0121                      struct snd_pcm_runtime *runtime);
0122 void amdtp_dot_midi_trigger(struct amdtp_stream *s, unsigned int port,
0123               struct snd_rawmidi_substream *midi);
0124
0125 int snd_dg00x_transaction_register(struct snd_dg00x *dg00x);
0126 int snd_dg00x_transaction_reregister(struct snd_dg00x *dg00x);
0127 void snd_dg00x_transaction_unregister(struct snd_dg00x *dg00x);
0128
0129 extern const unsigned int snd_dg00x_stream_rates[SND_DG00X_RATE_COUNT];
0130 extern const unsigned int snd_dg00x_stream_pcm_channels[SND_DG00X_RATE_COUNT];
0131 int snd_dg00x_stream_get_external_rate(struct snd_dg00x *dg00x,
0132                        unsigned int *rate);
0133 int snd_dg00x_stream_get_local_rate(struct snd_dg00x *dg00x,
0134                     unsigned int *rate);
0135 int snd_dg00x_stream_set_local_rate(struct snd_dg00x *dg00x, unsigned int rate);
0136 int snd_dg00x_stream_get_clock(struct snd_dg00x *dg00x,
0137                    enum snd_dg00x_clock *clock);
0138 int snd_dg00x_stream_check_external_clock(struct snd_dg00x *dg00x,
0139                       bool *detect);
0140 int snd_dg00x_stream_init_duplex(struct snd_dg00x *dg00x);
0141 int snd_dg00x_stream_reserve_duplex(struct snd_dg00x *dg00x, unsigned int rate,
0142                     unsigned int frames_per_period,
0143                     unsigned int frames_per_buffer);
0144 int snd_dg00x_stream_start_duplex(struct snd_dg00x *dg00x);
0145 void snd_dg00x_stream_stop_duplex(struct snd_dg00x *dg00x);
0146 void snd_dg00x_stream_update_duplex(struct snd_dg00x *dg00x);
0147 void snd_dg00x_stream_destroy_duplex(struct snd_dg00x *dg00x);
0148
0149 void snd_dg00x_stream_lock_changed(struct snd_dg00x *dg00x);
0150 int snd_dg00x_stream_lock_try(struct snd_dg00x *dg00x);
0151 void snd_dg00x_stream_lock_release(struct snd_dg00x *dg00x);
0152
0153 void snd_dg00x_proc_init(struct snd_dg00x *dg00x);
0154
0155 int snd_dg00x_create_pcm_devices(struct snd_dg00x *dg00x);
0156
0157 int snd_dg00x_create_midi_devices(struct snd_dg00x *dg00x);
0158
0159 int snd_dg00x_create_hwdep_device(struct snd_dg00x *dg00x);
0160 #endif