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0001 /* SPDX-License-Identifier: GPL-2.0 */ 0002 #ifndef SOUND_FIREWIRE_DICE_INTERFACE_H_INCLUDED 0003 #define SOUND_FIREWIRE_DICE_INTERFACE_H_INCLUDED 0004 0005 /* 0006 * DICE device interface definitions 0007 */ 0008 0009 /* 0010 * Generally, all registers can be read like memory, i.e., with quadlet read or 0011 * block read transactions with at least quadlet-aligned offset and length. 0012 * Writes are not allowed except where noted; quadlet-sized registers must be 0013 * written with a quadlet write transaction. 0014 * 0015 * All values are in big endian. The DICE firmware runs on a little-endian CPU 0016 * and just byte-swaps _all_ quadlets on the bus, so values without endianness 0017 * (e.g. strings) get scrambled and must be byte-swapped again by the driver. 0018 */ 0019 0020 /* 0021 * Streaming is handled by the "DICE driver" interface. Its registers are 0022 * located in this private address space. 0023 */ 0024 #define DICE_PRIVATE_SPACE 0xffffe0000000uLL 0025 0026 /* 0027 * The registers are organized in several sections, which are organized 0028 * separately to allow them to be extended individually. Whether a register is 0029 * supported can be detected by checking its offset against its section's size. 0030 * 0031 * The section offset values are relative to DICE_PRIVATE_SPACE; the offset/ 0032 * size values are measured in quadlets. Read-only. 0033 */ 0034 #define DICE_GLOBAL_OFFSET 0x00 0035 #define DICE_GLOBAL_SIZE 0x04 0036 #define DICE_TX_OFFSET 0x08 0037 #define DICE_TX_SIZE 0x0c 0038 #define DICE_RX_OFFSET 0x10 0039 #define DICE_RX_SIZE 0x14 0040 #define DICE_EXT_SYNC_OFFSET 0x18 0041 #define DICE_EXT_SYNC_SIZE 0x1c 0042 #define DICE_UNUSED2_OFFSET 0x20 0043 #define DICE_UNUSED2_SIZE 0x24 0044 0045 /* 0046 * Global settings. 0047 */ 0048 0049 /* 0050 * Stores the full 64-bit address (node ID and offset in the node's address 0051 * space) where the device will send notifications. Must be changed with 0052 * a compare/swap transaction by the owner. This register is automatically 0053 * cleared on a bus reset. 0054 */ 0055 #define GLOBAL_OWNER 0x000 0056 #define OWNER_NO_OWNER 0xffff000000000000uLL 0057 #define OWNER_NODE_SHIFT 48 0058 0059 /* 0060 * A bitmask with asynchronous events; read-only. When any event(s) happen, 0061 * the bits of previous events are cleared, and the value of this register is 0062 * also written to the address stored in the owner register. 0063 */ 0064 #define GLOBAL_NOTIFICATION 0x008 0065 /* Some registers in the Rx/Tx sections may have changed. */ 0066 #define NOTIFY_RX_CFG_CHG 0x00000001 0067 #define NOTIFY_TX_CFG_CHG 0x00000002 0068 /* Lock status of the current clock source may have changed. */ 0069 #define NOTIFY_LOCK_CHG 0x00000010 0070 /* Write to the clock select register has been finished. */ 0071 #define NOTIFY_CLOCK_ACCEPTED 0x00000020 0072 /* Lock status of some clock source has changed. */ 0073 #define NOTIFY_EXT_STATUS 0x00000040 0074 /* Other bits may be used for device-specific events. */ 0075 0076 /* 0077 * A name that can be customized for each device; read/write. Padded with zero 0078 * bytes. Quadlets are byte-swapped. The encoding is whatever the host driver 0079 * happens to be using. 0080 */ 0081 #define GLOBAL_NICK_NAME 0x00c 0082 #define NICK_NAME_SIZE 64 0083 0084 /* 0085 * The current sample rate and clock source; read/write. Whether a clock 0086 * source or sample rate is supported is device-specific; the internal clock 0087 * source is always available. Low/mid/high = up to 48/96/192 kHz. This 0088 * register can be changed even while streams are running. 0089 */ 0090 #define GLOBAL_CLOCK_SELECT 0x04c 0091 #define CLOCK_SOURCE_MASK 0x000000ff 0092 #define CLOCK_SOURCE_AES1 0x00000000 0093 #define CLOCK_SOURCE_AES2 0x00000001 0094 #define CLOCK_SOURCE_AES3 0x00000002 0095 #define CLOCK_SOURCE_AES4 0x00000003 0096 #define CLOCK_SOURCE_AES_ANY 0x00000004 0097 #define CLOCK_SOURCE_ADAT 0x00000005 0098 #define CLOCK_SOURCE_TDIF 0x00000006 0099 #define CLOCK_SOURCE_WC 0x00000007 0100 #define CLOCK_SOURCE_ARX1 0x00000008 0101 #define CLOCK_SOURCE_ARX2 0x00000009 0102 #define CLOCK_SOURCE_ARX3 0x0000000a 0103 #define CLOCK_SOURCE_ARX4 0x0000000b 0104 #define CLOCK_SOURCE_INTERNAL 0x0000000c 0105 #define CLOCK_RATE_MASK 0x0000ff00 0106 #define CLOCK_RATE_32000 0x00000000 0107 #define CLOCK_RATE_44100 0x00000100 0108 #define CLOCK_RATE_48000 0x00000200 0109 #define CLOCK_RATE_88200 0x00000300 0110 #define CLOCK_RATE_96000 0x00000400 0111 #define CLOCK_RATE_176400 0x00000500 0112 #define CLOCK_RATE_192000 0x00000600 0113 #define CLOCK_RATE_ANY_LOW 0x00000700 0114 #define CLOCK_RATE_ANY_MID 0x00000800 0115 #define CLOCK_RATE_ANY_HIGH 0x00000900 0116 #define CLOCK_RATE_NONE 0x00000a00 0117 #define CLOCK_RATE_SHIFT 8 0118 0119 /* 0120 * Enable streaming; read/write. Writing a non-zero value (re)starts all 0121 * streams that have a valid iso channel set; zero stops all streams. The 0122 * streams' parameters must be configured before starting. This register is 0123 * automatically cleared on a bus reset. 0124 */ 0125 #define GLOBAL_ENABLE 0x050 0126 0127 /* 0128 * Status of the sample clock; read-only. 0129 */ 0130 #define GLOBAL_STATUS 0x054 0131 /* The current clock source is locked. */ 0132 #define STATUS_SOURCE_LOCKED 0x00000001 0133 /* The actual sample rate; CLOCK_RATE_32000-_192000 or _NONE. */ 0134 #define STATUS_NOMINAL_RATE_MASK 0x0000ff00 0135 0136 /* 0137 * Status of all clock sources; read-only. 0138 */ 0139 #define GLOBAL_EXTENDED_STATUS 0x058 0140 /* 0141 * The _LOCKED bits always show the current status; any change generates 0142 * a notification. 0143 */ 0144 #define EXT_STATUS_AES1_LOCKED 0x00000001 0145 #define EXT_STATUS_AES2_LOCKED 0x00000002 0146 #define EXT_STATUS_AES3_LOCKED 0x00000004 0147 #define EXT_STATUS_AES4_LOCKED 0x00000008 0148 #define EXT_STATUS_ADAT_LOCKED 0x00000010 0149 #define EXT_STATUS_TDIF_LOCKED 0x00000020 0150 #define EXT_STATUS_ARX1_LOCKED 0x00000040 0151 #define EXT_STATUS_ARX2_LOCKED 0x00000080 0152 #define EXT_STATUS_ARX3_LOCKED 0x00000100 0153 #define EXT_STATUS_ARX4_LOCKED 0x00000200 0154 #define EXT_STATUS_WC_LOCKED 0x00000400 0155 /* 0156 * The _SLIP bits do not generate notifications; a set bit indicates that an 0157 * error occurred since the last time when this register was read with 0158 * a quadlet read transaction. 0159 */ 0160 #define EXT_STATUS_AES1_SLIP 0x00010000 0161 #define EXT_STATUS_AES2_SLIP 0x00020000 0162 #define EXT_STATUS_AES3_SLIP 0x00040000 0163 #define EXT_STATUS_AES4_SLIP 0x00080000 0164 #define EXT_STATUS_ADAT_SLIP 0x00100000 0165 #define EXT_STATUS_TDIF_SLIP 0x00200000 0166 #define EXT_STATUS_ARX1_SLIP 0x00400000 0167 #define EXT_STATUS_ARX2_SLIP 0x00800000 0168 #define EXT_STATUS_ARX3_SLIP 0x01000000 0169 #define EXT_STATUS_ARX4_SLIP 0x02000000 0170 #define EXT_STATUS_WC_SLIP 0x04000000 0171 0172 /* 0173 * The measured rate of the current clock source, in Hz; read-only. 0174 */ 0175 #define GLOBAL_SAMPLE_RATE 0x05c 0176 0177 /* 0178 * Some old firmware versions do not have the following global registers. 0179 * Windows drivers produced by TCAT lost backward compatibility in its 0180 * early release because they can handle firmware only which supports the 0181 * following registers. 0182 */ 0183 0184 /* 0185 * The version of the DICE driver specification that this device conforms to; 0186 * read-only. 0187 */ 0188 #define GLOBAL_VERSION 0x060 0189 0190 /* 0191 * Supported sample rates and clock sources; read-only. 0192 */ 0193 #define GLOBAL_CLOCK_CAPABILITIES 0x064 0194 #define CLOCK_CAP_RATE_32000 0x00000001 0195 #define CLOCK_CAP_RATE_44100 0x00000002 0196 #define CLOCK_CAP_RATE_48000 0x00000004 0197 #define CLOCK_CAP_RATE_88200 0x00000008 0198 #define CLOCK_CAP_RATE_96000 0x00000010 0199 #define CLOCK_CAP_RATE_176400 0x00000020 0200 #define CLOCK_CAP_RATE_192000 0x00000040 0201 #define CLOCK_CAP_SOURCE_AES1 0x00010000 0202 #define CLOCK_CAP_SOURCE_AES2 0x00020000 0203 #define CLOCK_CAP_SOURCE_AES3 0x00040000 0204 #define CLOCK_CAP_SOURCE_AES4 0x00080000 0205 #define CLOCK_CAP_SOURCE_AES_ANY 0x00100000 0206 #define CLOCK_CAP_SOURCE_ADAT 0x00200000 0207 #define CLOCK_CAP_SOURCE_TDIF 0x00400000 0208 #define CLOCK_CAP_SOURCE_WC 0x00800000 0209 #define CLOCK_CAP_SOURCE_ARX1 0x01000000 0210 #define CLOCK_CAP_SOURCE_ARX2 0x02000000 0211 #define CLOCK_CAP_SOURCE_ARX3 0x04000000 0212 #define CLOCK_CAP_SOURCE_ARX4 0x08000000 0213 #define CLOCK_CAP_SOURCE_INTERNAL 0x10000000 0214 0215 /* 0216 * Names of all clock sources; read-only. Quadlets are byte-swapped. Names 0217 * are separated with one backslash, the list is terminated with two 0218 * backslashes. Unused clock sources are included. 0219 */ 0220 #define GLOBAL_CLOCK_SOURCE_NAMES 0x068 0221 #define CLOCK_SOURCE_NAMES_SIZE 256 0222 0223 /* 0224 * Capture stream settings. This section includes the number/size registers 0225 * and the registers of all streams. 0226 */ 0227 0228 /* 0229 * The number of supported capture streams; read-only. 0230 */ 0231 #define TX_NUMBER 0x000 0232 0233 /* 0234 * The size of one stream's register block, in quadlets; read-only. The 0235 * registers of the first stream follow immediately afterwards; the registers 0236 * of the following streams are offset by this register's value. 0237 */ 0238 #define TX_SIZE 0x004 0239 0240 /* 0241 * The isochronous channel number on which packets are sent, or -1 if the 0242 * stream is not to be used; read/write. 0243 */ 0244 #define TX_ISOCHRONOUS 0x008 0245 0246 /* 0247 * The number of audio channels; read-only. There will be one quadlet per 0248 * channel; the first channel is the first quadlet in a data block. 0249 */ 0250 #define TX_NUMBER_AUDIO 0x00c 0251 0252 /* 0253 * The number of MIDI ports, 0-8; read-only. If > 0, there will be one 0254 * additional quadlet in each data block, following the audio quadlets. 0255 */ 0256 #define TX_NUMBER_MIDI 0x010 0257 0258 /* 0259 * The speed at which the packets are sent, SCODE_100-_400; read/write. 0260 * SCODE_800 is only available in Dice III. 0261 */ 0262 #define TX_SPEED 0x014 0263 0264 /* 0265 * Names of all audio channels; read-only. Quadlets are byte-swapped. Names 0266 * are separated with one backslash, the list is terminated with two 0267 * backslashes. 0268 */ 0269 #define TX_NAMES 0x018 0270 #define TX_NAMES_SIZE 256 0271 0272 /* 0273 * Audio IEC60958 capabilities; read-only. Bitmask with one bit per audio 0274 * channel. 0275 */ 0276 #define TX_AC3_CAPABILITIES 0x118 0277 0278 /* 0279 * Send audio data with IEC60958 label; read/write. Bitmask with one bit per 0280 * audio channel. This register can be changed even while the stream is 0281 * running. 0282 */ 0283 #define TX_AC3_ENABLE 0x11c 0284 0285 /* 0286 * Playback stream settings. This section includes the number/size registers 0287 * and the registers of all streams. 0288 */ 0289 0290 /* 0291 * The number of supported playback streams; read-only. 0292 */ 0293 #define RX_NUMBER 0x000 0294 0295 /* 0296 * The size of one stream's register block, in quadlets; read-only. The 0297 * registers of the first stream follow immediately afterwards; the registers 0298 * of the following streams are offset by this register's value. 0299 */ 0300 #define RX_SIZE 0x004 0301 0302 /* 0303 * The isochronous channel number on which packets are received, or -1 if the 0304 * stream is not to be used; read/write. 0305 */ 0306 #define RX_ISOCHRONOUS 0x008 0307 0308 /* 0309 * Index of first quadlet to be interpreted; read/write. If > 0, that many 0310 * quadlets at the beginning of each data block will be ignored, and all the 0311 * audio and MIDI quadlets will follow. 0312 */ 0313 #define RX_SEQ_START 0x00c 0314 0315 /* 0316 * The number of audio channels; read-only. There will be one quadlet per 0317 * channel. 0318 */ 0319 #define RX_NUMBER_AUDIO 0x010 0320 0321 /* 0322 * The number of MIDI ports, 0-8; read-only. If > 0, there will be one 0323 * additional quadlet in each data block, following the audio quadlets. 0324 */ 0325 #define RX_NUMBER_MIDI 0x014 0326 0327 /* 0328 * Names of all audio channels; read-only. Quadlets are byte-swapped. Names 0329 * are separated with one backslash, the list is terminated with two 0330 * backslashes. 0331 */ 0332 #define RX_NAMES 0x018 0333 #define RX_NAMES_SIZE 256 0334 0335 /* 0336 * Audio IEC60958 capabilities; read-only. Bitmask with one bit per audio 0337 * channel. 0338 */ 0339 #define RX_AC3_CAPABILITIES 0x118 0340 0341 /* 0342 * Receive audio data with IEC60958 label; read/write. Bitmask with one bit 0343 * per audio channel. This register can be changed even while the stream is 0344 * running. 0345 */ 0346 #define RX_AC3_ENABLE 0x11c 0347 0348 /* 0349 * Extended synchronization information. 0350 * This section can be read completely with a block read request. 0351 */ 0352 0353 /* 0354 * Current clock source; read-only. 0355 */ 0356 #define EXT_SYNC_CLOCK_SOURCE 0x000 0357 0358 /* 0359 * Clock source is locked (boolean); read-only. 0360 */ 0361 #define EXT_SYNC_LOCKED 0x004 0362 0363 /* 0364 * Current sample rate (CLOCK_RATE_* >> CLOCK_RATE_SHIFT), _32000-_192000 or 0365 * _NONE; read-only. 0366 */ 0367 #define EXT_SYNC_RATE 0x008 0368 0369 /* 0370 * ADAT user data bits; read-only. 0371 */ 0372 #define EXT_SYNC_ADAT_USER_DATA 0x00c 0373 /* The data bits, if available. */ 0374 #define ADAT_USER_DATA_MASK 0x0f 0375 /* The data bits are not available. */ 0376 #define ADAT_USER_DATA_NO_DATA 0x10 0377 0378 #endif
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