sound/arm/pxa2xx-ac97-regs.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef __ASM_ARCH_REGS_AC97_H
0003 #define __ASM_ARCH_REGS_AC97_H
0004
0005 /*
0006  * AC97 Controller registers
0007  */
0008
0009 #define POCR        (0x0000)    /* PCM Out Control Register */
0010 #define POCR_FEIE   (1 << 3)    /* FIFO Error Interrupt Enable */
0011 #define POCR_FSRIE  (1 << 1)    /* FIFO Service Request Interrupt Enable */
0012
0013 #define PICR        (0x0004)    /* PCM In Control Register */
0014 #define PICR_FEIE   (1 << 3)    /* FIFO Error Interrupt Enable */
0015 #define PICR_FSRIE  (1 << 1)    /* FIFO Service Request Interrupt Enable */
0016
0017 #define MCCR        (0x0008)    /* Mic In Control Register */
0018 #define MCCR_FEIE   (1 << 3)    /* FIFO Error Interrupt Enable */
0019 #define MCCR_FSRIE  (1 << 1)    /* FIFO Service Request Interrupt Enable */
0020
0021 #define GCR     (0x000C)     /* Global Control Register */
0022 #ifdef CONFIG_PXA3xx
0023 #define GCR_CLKBPB  (1 << 31)   /* Internal clock enable */
0024 #endif
0025 #define GCR_nDMAEN  (1 << 24)   /* non DMA Enable */
0026 #define GCR_CDONE_IE    (1 << 19)   /* Command Done Interrupt Enable */
0027 #define GCR_SDONE_IE    (1 << 18)   /* Status Done Interrupt Enable */
0028 #define GCR_SECRDY_IEN  (1 << 9)    /* Secondary Ready Interrupt Enable */
0029 #define GCR_PRIRDY_IEN  (1 << 8)    /* Primary Ready Interrupt Enable */
0030 #define GCR_SECRES_IEN  (1 << 5)    /* Secondary Resume Interrupt Enable */
0031 #define GCR_PRIRES_IEN  (1 << 4)    /* Primary Resume Interrupt Enable */
0032 #define GCR_ACLINK_OFF  (1 << 3)    /* AC-link Shut Off */
0033 #define GCR_WARM_RST    (1 << 2)    /* AC97 Warm Reset */
0034 #define GCR_COLD_RST    (1 << 1)    /* AC'97 Cold Reset (0 = active) */
0035 #define GCR_GIE     (1 << 0)    /* Codec GPI Interrupt Enable */
0036
0037 #define POSR        (0x0010)    /* PCM Out Status Register */
0038 #define POSR_FIFOE  (1 << 4)    /* FIFO error */
0039 #define POSR_FSR    (1 << 2)    /* FIFO Service Request */
0040
0041 #define PISR        (0x0014)    /* PCM In Status Register */
0042 #define PISR_FIFOE  (1 << 4)    /* FIFO error */
0043 #define PISR_EOC    (1 << 3)    /* DMA End-of-Chain (exclusive clear) */
0044 #define PISR_FSR    (1 << 2)    /* FIFO Service Request */
0045
0046 #define MCSR        (0x0018)    /* Mic In Status Register */
0047 #define MCSR_FIFOE  (1 << 4)    /* FIFO error */
0048 #define MCSR_EOC    (1 << 3)    /* DMA End-of-Chain (exclusive clear) */
0049 #define MCSR_FSR    (1 << 2)    /* FIFO Service Request */
0050
0051 #define GSR     (0x001C)    /* Global Status Register */
0052 #define GSR_CDONE   (1 << 19)   /* Command Done */
0053 #define GSR_SDONE   (1 << 18)   /* Status Done */
0054 #define GSR_RDCS    (1 << 15)   /* Read Completion Status */
0055 #define GSR_BIT3SLT12   (1 << 14)   /* Bit 3 of slot 12 */
0056 #define GSR_BIT2SLT12   (1 << 13)   /* Bit 2 of slot 12 */
0057 #define GSR_BIT1SLT12   (1 << 12)   /* Bit 1 of slot 12 */
0058 #define GSR_SECRES  (1 << 11)   /* Secondary Resume Interrupt */
0059 #define GSR_PRIRES  (1 << 10)   /* Primary Resume Interrupt */
0060 #define GSR_SCR     (1 << 9)    /* Secondary Codec Ready */
0061 #define GSR_PCR     (1 << 8)    /*  Primary Codec Ready */
0062 #define GSR_MCINT   (1 << 7)    /* Mic In Interrupt */
0063 #define GSR_POINT   (1 << 6)    /* PCM Out Interrupt */
0064 #define GSR_PIINT   (1 << 5)    /* PCM In Interrupt */
0065 #define GSR_ACOFFD  (1 << 3)    /* AC-link Shut Off Done */
0066 #define GSR_MOINT   (1 << 2)    /* Modem Out Interrupt */
0067 #define GSR_MIINT   (1 << 1)    /* Modem In Interrupt */
0068 #define GSR_GSCI    (1 << 0)    /* Codec GPI Status Change Interrupt */
0069
0070 #define CAR     (0x0020)    /* CODEC Access Register */
0071 #define CAR_CAIP    (1 << 0)    /* Codec Access In Progress */
0072
0073 #define PCDR        (0x0040)    /* PCM FIFO Data Register */
0074 #define MCDR        (0x0060)    /* Mic-in FIFO Data Register */
0075
0076 #define MOCR        (0x0100)    /* Modem Out Control Register */
0077 #define MOCR_FEIE   (1 << 3)    /* FIFO Error */
0078 #define MOCR_FSRIE  (1 << 1)    /* FIFO Service Request Interrupt Enable */
0079
0080 #define MICR        (0x0108)    /* Modem In Control Register */
0081 #define MICR_FEIE   (1 << 3)    /* FIFO Error */
0082 #define MICR_FSRIE  (1 << 1)    /* FIFO Service Request Interrupt Enable */
0083
0084 #define MOSR        (0x0110)    /* Modem Out Status Register */
0085 #define MOSR_FIFOE  (1 << 4)    /* FIFO error */
0086 #define MOSR_FSR    (1 << 2)    /* FIFO Service Request */
0087
0088 #define MISR        (0x0118)    /* Modem In Status Register */
0089 #define MISR_FIFOE  (1 << 4)    /* FIFO error */
0090 #define MISR_EOC    (1 << 3)    /* DMA End-of-Chain (exclusive clear) */
0091 #define MISR_FSR    (1 << 2)    /* FIFO Service Request */
0092
0093 #define MODR        (0x0140)    /* Modem FIFO Data Register */
0094
0095 #define PAC_REG_BASE    (0x0200)    /* Primary Audio Codec */
0096 #define SAC_REG_BASE    (0x0300)    /* Secondary Audio Codec */
0097 #define PMC_REG_BASE    (0x0400)    /* Primary Modem Codec */
0098 #define SMC_REG_BASE    (0x0500)    /* Secondary Modem Codec */
0099
0100 #endif /* __ASM_ARCH_REGS_AC97_H */