sound/arm/aaci.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  *  linux/sound/arm/aaci.c - ARM PrimeCell AACI PL041 driver
0004  *
0005  *  Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
0006  */
0007 #ifndef AACI_H
0008 #define AACI_H
0009
0010 /*
0011  * Control and status register offsets
0012  *  P39.
0013  */
0014 #define AACI_CSCH1  0x000
0015 #define AACI_CSCH2  0x014
0016 #define AACI_CSCH3  0x028
0017 #define AACI_CSCH4  0x03c
0018
0019 #define AACI_RXCR   0x000   /* 29 bits Control Rx FIFO */
0020 #define AACI_TXCR   0x004   /* 17 bits Control Tx FIFO */
0021 #define AACI_SR     0x008   /* 12 bits Status */
0022 #define AACI_ISR    0x00c   /* 7 bits  Int Status */
0023 #define AACI_IE     0x010   /* 7 bits  Int Enable */
0024
0025 /*
0026  * Other registers
0027  */
0028 #define AACI_SL1RX  0x050
0029 #define AACI_SL1TX  0x054
0030 #define AACI_SL2RX  0x058
0031 #define AACI_SL2TX  0x05c
0032 #define AACI_SL12RX 0x060
0033 #define AACI_SL12TX 0x064
0034 #define AACI_SLFR   0x068   /* slot flags */
0035 #define AACI_SLISTAT    0x06c   /* slot interrupt status */
0036 #define AACI_SLIEN  0x070   /* slot interrupt enable */
0037 #define AACI_INTCLR 0x074   /* interrupt clear */
0038 #define AACI_MAINCR 0x078   /* main control */
0039 #define AACI_RESET  0x07c   /* reset control */
0040 #define AACI_SYNC   0x080   /* sync control */
0041 #define AACI_ALLINTS    0x084   /* all fifo interrupt status */
0042 #define AACI_MAINFR 0x088   /* main flag register */
0043 #define AACI_DR1    0x090   /* data read/written fifo 1 */
0044 #define AACI_DR2    0x0b0   /* data read/written fifo 2 */
0045 #define AACI_DR3    0x0d0   /* data read/written fifo 3 */
0046 #define AACI_DR4    0x0f0   /* data read/written fifo 4 */
0047
0048 /*
0049  * TX/RX fifo control register (CR). P48
0050  */
0051 #define CR_FEN      (1 << 16)   /* fifo enable */
0052 #define CR_COMPACT  (1 << 15)   /* compact mode */
0053 #define CR_SZ16     (0 << 13)   /* 16 bits */
0054 #define CR_SZ18     (1 << 13)   /* 18 bits */
0055 #define CR_SZ20     (2 << 13)   /* 20 bits */
0056 #define CR_SZ12     (3 << 13)   /* 12 bits */
0057 #define CR_SL12     (1 << 12)
0058 #define CR_SL11     (1 << 11)
0059 #define CR_SL10     (1 << 10)
0060 #define CR_SL9      (1 << 9)
0061 #define CR_SL8      (1 << 8)
0062 #define CR_SL7      (1 << 7)
0063 #define CR_SL6      (1 << 6)
0064 #define CR_SL5      (1 << 5)
0065 #define CR_SL4      (1 << 4)
0066 #define CR_SL3      (1 << 3)
0067 #define CR_SL2      (1 << 2)
0068 #define CR_SL1      (1 << 1)
0069 #define CR_EN       (1 << 0)    /* transmit enable */
0070
0071 /*
0072  * status register bits. P49
0073  */
0074 #define SR_RXTOFE   (1 << 11)   /* rx timeout fifo empty */
0075 #define SR_TXTO     (1 << 10)   /* rx timeout fifo nonempty */
0076 #define SR_TXU      (1 << 9)    /* tx underrun */
0077 #define SR_RXO      (1 << 8)    /* rx overrun */
0078 #define SR_TXB      (1 << 7)    /* tx busy */
0079 #define SR_RXB      (1 << 6)    /* rx busy */
0080 #define SR_TXFF     (1 << 5)    /* tx fifo full */
0081 #define SR_RXFF     (1 << 4)    /* rx fifo full */
0082 #define SR_TXHE     (1 << 3)    /* tx fifo half empty */
0083 #define SR_RXHF     (1 << 2)    /* rx fifo half full */
0084 #define SR_TXFE     (1 << 1)    /* tx fifo empty */
0085 #define SR_RXFE     (1 << 0)    /* rx fifo empty */
0086
0087 /*
0088  * interrupt status register bits.
0089  */
0090 #define ISR_RXTOFEINTR  (1 << 6)    /* rx fifo empty */
0091 #define ISR_URINTR  (1 << 5)    /* tx underflow */
0092 #define ISR_ORINTR  (1 << 4)    /* rx overflow */
0093 #define ISR_RXINTR  (1 << 3)    /* rx fifo */
0094 #define ISR_TXINTR  (1 << 2)    /* tx fifo intr */
0095 #define ISR_RXTOINTR    (1 << 1)    /* tx timeout */
0096 #define ISR_TXCINTR (1 << 0)    /* tx complete */
0097
0098 /*
0099  * interrupt enable register bits.
0100  */
0101 #define IE_RXTOIE   (1 << 6)
0102 #define IE_URIE     (1 << 5)
0103 #define IE_ORIE     (1 << 4)
0104 #define IE_RXIE     (1 << 3)
0105 #define IE_TXIE     (1 << 2)
0106 #define IE_RXTIE    (1 << 1)
0107 #define IE_TXCIE    (1 << 0)
0108
0109 /*
0110  * interrupt status. P51
0111  */
0112 #define ISR_RXTOFE  (1 << 6)    /* rx timeout fifo empty */
0113 #define ISR_UR      (1 << 5)    /* tx fifo underrun */
0114 #define ISR_OR      (1 << 4)    /* rx fifo overrun */
0115 #define ISR_RX      (1 << 3)    /* rx interrupt status */
0116 #define ISR_TX      (1 << 2)    /* tx interrupt status */
0117 #define ISR_RXTO    (1 << 1)    /* rx timeout */
0118 #define ISR_TXC     (1 << 0)    /* tx complete */
0119
0120 /*
0121  * interrupt enable. P52
0122  */
0123 #define IE_RXTOFE   (1 << 6)    /* rx timeout fifo empty */
0124 #define IE_UR       (1 << 5)    /* tx fifo underrun */
0125 #define IE_OR       (1 << 4)    /* rx fifo overrun */
0126 #define IE_RX       (1 << 3)    /* rx interrupt status */
0127 #define IE_TX       (1 << 2)    /* tx interrupt status */
0128 #define IE_RXTO     (1 << 1)    /* rx timeout */
0129 #define IE_TXC      (1 << 0)    /* tx complete */
0130
0131 /*
0132  * slot flag register bits. P56
0133  */
0134 #define SLFR_RWIS   (1 << 13)   /* raw wake-up interrupt status */
0135 #define SLFR_RGPIOINTR  (1 << 12)   /* raw gpio interrupt */
0136 #define SLFR_12TXE  (1 << 11)   /* slot 12 tx empty */
0137 #define SLFR_12RXV  (1 << 10)   /* slot 12 rx valid */
0138 #define SLFR_2TXE   (1 << 9)    /* slot 2 tx empty */
0139 #define SLFR_2RXV   (1 << 8)    /* slot 2 rx valid */
0140 #define SLFR_1TXE   (1 << 7)    /* slot 1 tx empty */
0141 #define SLFR_1RXV   (1 << 6)    /* slot 1 rx valid */
0142 #define SLFR_12TXB  (1 << 5)    /* slot 12 tx busy */
0143 #define SLFR_12RXB  (1 << 4)    /* slot 12 rx busy */
0144 #define SLFR_2TXB   (1 << 3)    /* slot 2 tx busy */
0145 #define SLFR_2RXB   (1 << 2)    /* slot 2 rx busy */
0146 #define SLFR_1TXB   (1 << 1)    /* slot 1 tx busy */
0147 #define SLFR_1RXB   (1 << 0)    /* slot 1 rx busy */
0148
0149 /*
0150  * Interrupt clear register.
0151  */
0152 #define ICLR_RXTOFEC4   (1 << 12)
0153 #define ICLR_RXTOFEC3   (1 << 11)
0154 #define ICLR_RXTOFEC2   (1 << 10)
0155 #define ICLR_RXTOFEC1   (1 << 9)
0156 #define ICLR_TXUEC4 (1 << 8)
0157 #define ICLR_TXUEC3 (1 << 7)
0158 #define ICLR_TXUEC2 (1 << 6)
0159 #define ICLR_TXUEC1 (1 << 5)
0160 #define ICLR_RXOEC4 (1 << 4)
0161 #define ICLR_RXOEC3 (1 << 3)
0162 #define ICLR_RXOEC2 (1 << 2)
0163 #define ICLR_RXOEC1 (1 << 1)
0164 #define ICLR_WISC   (1 << 0)
0165
0166 /*
0167  * Main control register bits. P62
0168  */
0169 #define MAINCR_SCRA(x)  ((x) << 10) /* secondary codec reg access */
0170 #define MAINCR_DMAEN    (1 << 9)    /* dma enable */
0171 #define MAINCR_SL12TXEN (1 << 8)    /* slot 12 transmit enable */
0172 #define MAINCR_SL12RXEN (1 << 7)    /* slot 12 receive enable */
0173 #define MAINCR_SL2TXEN  (1 << 6)    /* slot 2 transmit enable */
0174 #define MAINCR_SL2RXEN  (1 << 5)    /* slot 2 receive enable */
0175 #define MAINCR_SL1TXEN  (1 << 4)    /* slot 1 transmit enable */
0176 #define MAINCR_SL1RXEN  (1 << 3)    /* slot 1 receive enable */
0177 #define MAINCR_LPM  (1 << 2)    /* low power mode */
0178 #define MAINCR_LOOPBK   (1 << 1)    /* loopback */
0179 #define MAINCR_IE   (1 << 0)    /* aaci interface enable */
0180
0181 /*
0182  * Reset register bits. P65
0183  */
0184 #define RESET_NRST  (1 << 0)
0185
0186 /*
0187  * Sync register bits. P65
0188  */
0189 #define SYNC_FORCE  (1 << 0)
0190
0191 /*
0192  * Main flag register bits. P66
0193  */
0194 #define MAINFR_TXB  (1 << 1)    /* transmit busy */
0195 #define MAINFR_RXB  (1 << 0)    /* receive busy */
0196
0197
0198
0199 struct aaci_runtime {
0200     void            __iomem *base;
0201     void            __iomem *fifo;
0202     spinlock_t      lock;
0203
0204     struct ac97_pcm     *pcm;
0205     int         pcm_open;
0206
0207     u32         cr;
0208     struct snd_pcm_substream    *substream;
0209
0210     unsigned int        period; /* byte size of a "period" */
0211
0212     /*
0213      * PIO support
0214      */
0215     void            *start;
0216     void            *end;
0217     void            *ptr;
0218     int         bytes;
0219     unsigned int        fifo_bytes;
0220 };
0221
0222 struct aaci {
0223     struct amba_device  *dev;
0224     struct snd_card     *card;
0225     void            __iomem *base;
0226     unsigned int        fifo_depth;
0227     unsigned int        users;
0228     struct mutex        irq_lock;
0229
0230     /* AC'97 */
0231     struct mutex        ac97_sem;
0232     struct snd_ac97_bus *ac97_bus;
0233     struct snd_ac97     *ac97;
0234
0235     u32         maincr;
0236
0237     struct aaci_runtime playback;
0238     struct aaci_runtime capture;
0239
0240     struct snd_pcm      *pcm;
0241 };
0242
0243 #define ACSTREAM_FRONT      0
0244 #define ACSTREAM_SURROUND   1
0245 #define ACSTREAM_LFE        2
0246
0247 #endif