soundbus/i2sbus/interface.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * i2sbus driver -- interface register definitions
0004  *
0005  * Copyright 2006 Johannes Berg <johannes@sipsolutions.net>
0006  */
0007 #ifndef __I2SBUS_INTERFACE_H
0008 #define __I2SBUS_INTERFACE_H
0009
0010 /* i2s bus control registers, at least what we know about them */
0011
0012 #define __PAD(m,n) u8 __pad##m[n]
0013 #define _PAD(line, n) __PAD(line, n)
0014 #define PAD(n) _PAD(__LINE__, (n))
0015 struct i2s_interface_regs {
0016     __le32 intr_ctl;    /* 0x00 */
0017     PAD(12);
0018     __le32 serial_format;   /* 0x10 */
0019     PAD(12);
0020     __le32 codec_msg_out;   /* 0x20 */
0021     PAD(12);
0022     __le32 codec_msg_in;    /* 0x30 */
0023     PAD(12);
0024     __le32 frame_count; /* 0x40 */
0025     PAD(12);
0026     __le32 frame_match; /* 0x50 */
0027     PAD(12);
0028     __le32 data_word_sizes; /* 0x60 */
0029     PAD(12);
0030     __le32 peak_level_sel;  /* 0x70 */
0031     PAD(12);
0032     __le32 peak_level_in0;  /* 0x80 */
0033     PAD(12);
0034     __le32 peak_level_in1;  /* 0x90 */
0035     PAD(12);
0036     /* total size: 0x100 bytes */
0037 }  __attribute__((__packed__));
0038
0039 /* interrupt register is just a bitfield with
0040  * interrupt enable and pending bits */
0041 #define I2S_REG_INTR_CTL        0x00
0042 #   define I2S_INT_FRAME_COUNT      (1<<31)
0043 #   define I2S_PENDING_FRAME_COUNT      (1<<30)
0044 #   define I2S_INT_MESSAGE_FLAG     (1<<29)
0045 #   define I2S_PENDING_MESSAGE_FLAG     (1<<28)
0046 #   define I2S_INT_NEW_PEAK         (1<<27)
0047 #   define I2S_PENDING_NEW_PEAK     (1<<26)
0048 #   define I2S_INT_CLOCKS_STOPPED       (1<<25)
0049 #   define I2S_PENDING_CLOCKS_STOPPED   (1<<24)
0050 #   define I2S_INT_EXTERNAL_SYNC_ERROR  (1<<23)
0051 #   define I2S_PENDING_EXTERNAL_SYNC_ERROR  (1<<22)
0052 #   define I2S_INT_EXTERNAL_SYNC_OK     (1<<21)
0053 #   define I2S_PENDING_EXTERNAL_SYNC_OK (1<<20)
0054 #   define I2S_INT_NEW_SAMPLE_RATE      (1<<19)
0055 #   define I2S_PENDING_NEW_SAMPLE_RATE  (1<<18)
0056 #   define I2S_INT_STATUS_FLAG      (1<<17)
0057 #   define I2S_PENDING_STATUS_FLAG      (1<<16)
0058
0059 /* serial format register is more interesting :)
0060  * It contains:
0061  *  - clock source
0062  *  - MClk divisor
0063  *  - SClk divisor
0064  *  - SClk master flag
0065  *  - serial format (sony, i2s 64x, i2s 32x, dav, silabs)
0066  *  - external sample frequency interrupt (don't understand)
0067  *  - external sample frequency
0068  */
0069 #define I2S_REG_SERIAL_FORMAT       0x10
0070 /* clock source. You get either 18.432, 45.1584 or 49.1520 MHz */
0071 #   define I2S_SF_CLOCK_SOURCE_SHIFT    30
0072 #   define I2S_SF_CLOCK_SOURCE_MASK     (3<<I2S_SF_CLOCK_SOURCE_SHIFT)
0073 #   define I2S_SF_CLOCK_SOURCE_18MHz    (0<<I2S_SF_CLOCK_SOURCE_SHIFT)
0074 #   define I2S_SF_CLOCK_SOURCE_45MHz    (1<<I2S_SF_CLOCK_SOURCE_SHIFT)
0075 #   define I2S_SF_CLOCK_SOURCE_49MHz    (2<<I2S_SF_CLOCK_SOURCE_SHIFT)
0076 /* also, let's define the exact clock speeds here, in Hz */
0077 #define I2S_CLOCK_SPEED_18MHz   18432000
0078 #define I2S_CLOCK_SPEED_45MHz   45158400
0079 #define I2S_CLOCK_SPEED_49MHz   49152000
0080 /* MClk is the clock that drives the codec, usually called its 'system clock'.
0081  * It is derived by taking only every 'divisor' tick of the clock.
0082  */
0083 #   define I2S_SF_MCLKDIV_SHIFT     24
0084 #   define I2S_SF_MCLKDIV_MASK      (0x1F<<I2S_SF_MCLKDIV_SHIFT)
0085 #   define I2S_SF_MCLKDIV_1         (0x14<<I2S_SF_MCLKDIV_SHIFT)
0086 #   define I2S_SF_MCLKDIV_3         (0x13<<I2S_SF_MCLKDIV_SHIFT)
0087 #   define I2S_SF_MCLKDIV_5         (0x12<<I2S_SF_MCLKDIV_SHIFT)
0088 #   define I2S_SF_MCLKDIV_14        (0x0E<<I2S_SF_MCLKDIV_SHIFT)
0089 #   define I2S_SF_MCLKDIV_OTHER(div)    (((div/2-1)<<I2S_SF_MCLKDIV_SHIFT)&I2S_SF_MCLKDIV_MASK)
0090 static inline int i2s_sf_mclkdiv(int div, int *out)
0091 {
0092     int d;
0093
0094     switch(div) {
0095     case 1: *out |= I2S_SF_MCLKDIV_1; return 0;
0096     case 3: *out |= I2S_SF_MCLKDIV_3; return 0;
0097     case 5: *out |= I2S_SF_MCLKDIV_5; return 0;
0098     case 14: *out |= I2S_SF_MCLKDIV_14; return 0;
0099     default:
0100         if (div%2) return -1;
0101         d = div/2-1;
0102         if (d == 0x14 || d == 0x13 || d == 0x12 || d == 0x0E)
0103             return -1;
0104         *out |= I2S_SF_MCLKDIV_OTHER(div);
0105         return 0;
0106     }
0107 }
0108 /* SClk is the clock that drives the i2s wire bus. Note that it is
0109  * derived from the MClk above by taking only every 'divisor' tick
0110  * of MClk.
0111  */
0112 #   define I2S_SF_SCLKDIV_SHIFT     20
0113 #   define I2S_SF_SCLKDIV_MASK      (0xF<<I2S_SF_SCLKDIV_SHIFT)
0114 #   define I2S_SF_SCLKDIV_1         (8<<I2S_SF_SCLKDIV_SHIFT)
0115 #   define I2S_SF_SCLKDIV_3         (9<<I2S_SF_SCLKDIV_SHIFT)
0116 #   define I2S_SF_SCLKDIV_OTHER(div)    (((div/2-1)<<I2S_SF_SCLKDIV_SHIFT)&I2S_SF_SCLKDIV_MASK)
0117 static inline int i2s_sf_sclkdiv(int div, int *out)
0118 {
0119     int d;
0120
0121     switch(div) {
0122     case 1: *out |= I2S_SF_SCLKDIV_1; return 0;
0123     case 3: *out |= I2S_SF_SCLKDIV_3; return 0;
0124     default:
0125         if (div%2) return -1;
0126         d = div/2-1;
0127         if (d == 8 || d == 9) return -1;
0128         *out |= I2S_SF_SCLKDIV_OTHER(div);
0129         return 0;
0130     }
0131 }
0132 #   define I2S_SF_SCLK_MASTER       (1<<19)
0133 /* serial format is the way the data is put to the i2s wire bus */
0134 #   define I2S_SF_SERIAL_FORMAT_SHIFT   16
0135 #   define I2S_SF_SERIAL_FORMAT_MASK    (7<<I2S_SF_SERIAL_FORMAT_SHIFT)
0136 #   define I2S_SF_SERIAL_FORMAT_SONY    (0<<I2S_SF_SERIAL_FORMAT_SHIFT)
0137 #   define I2S_SF_SERIAL_FORMAT_I2S_64X (1<<I2S_SF_SERIAL_FORMAT_SHIFT)
0138 #   define I2S_SF_SERIAL_FORMAT_I2S_32X (2<<I2S_SF_SERIAL_FORMAT_SHIFT)
0139 #   define I2S_SF_SERIAL_FORMAT_I2S_DAV (4<<I2S_SF_SERIAL_FORMAT_SHIFT)
0140 #   define I2S_SF_SERIAL_FORMAT_I2S_SILABS  (5<<I2S_SF_SERIAL_FORMAT_SHIFT)
0141 /* unknown */
0142 #   define I2S_SF_EXT_SAMPLE_FREQ_INT_SHIFT 12
0143 #   define I2S_SF_EXT_SAMPLE_FREQ_INT_MASK  (0xF<<I2S_SF_SAMPLE_FREQ_INT_SHIFT)
0144 /* probably gives external frequency? */
0145 #   define I2S_SF_EXT_SAMPLE_FREQ_MASK  0xFFF
0146
0147 /* used to send codec messages, but how isn't clear */
0148 #define I2S_REG_CODEC_MSG_OUT       0x20
0149
0150 /* used to receive codec messages, but how isn't clear */
0151 #define I2S_REG_CODEC_MSG_IN        0x30
0152
0153 /* frame count reg isn't clear to me yet, but probably useful */
0154 #define I2S_REG_FRAME_COUNT     0x40
0155
0156 /* program to some value, and get interrupt if frame count reaches it */
0157 #define I2S_REG_FRAME_MATCH     0x50
0158
0159 /* this register describes how the bus transfers data */
0160 #define I2S_REG_DATA_WORD_SIZES     0x60
0161 /* number of interleaved input channels */
0162 #   define I2S_DWS_NUM_CHANNELS_IN_SHIFT    24
0163 #   define I2S_DWS_NUM_CHANNELS_IN_MASK (0x1F<<I2S_DWS_NUM_CHANNELS_IN_SHIFT)
0164 /* word size of input data */
0165 #   define I2S_DWS_DATA_IN_SIZE_SHIFT   16
0166 #   define I2S_DWS_DATA_IN_16BIT        (0<<I2S_DWS_DATA_IN_SIZE_SHIFT)
0167 #   define I2S_DWS_DATA_IN_24BIT        (3<<I2S_DWS_DATA_IN_SIZE_SHIFT)
0168 /* number of interleaved output channels */
0169 #   define I2S_DWS_NUM_CHANNELS_OUT_SHIFT   8
0170 #   define I2S_DWS_NUM_CHANNELS_OUT_MASK    (0x1F<<I2S_DWS_NUM_CHANNELS_OUT_SHIFT)
0171 /* word size of output data */
0172 #   define I2S_DWS_DATA_OUT_SIZE_SHIFT  0
0173 #   define I2S_DWS_DATA_OUT_16BIT       (0<<I2S_DWS_DATA_OUT_SIZE_SHIFT)
0174 #   define I2S_DWS_DATA_OUT_24BIT       (3<<I2S_DWS_DATA_OUT_SIZE_SHIFT)
0175
0176
0177 /* unknown */
0178 #define I2S_REG_PEAK_LEVEL_SEL      0x70
0179
0180 /* unknown */
0181 #define I2S_REG_PEAK_LEVEL_IN0      0x80
0182
0183 /* unknown */
0184 #define I2S_REG_PEAK_LEVEL_IN1      0x90
0185
0186 #endif /* __I2SBUS_INTERFACE_H */