0001 // SPDX-License-Identifier: GPL-2.0
0002 /dts-v1/;
0003
0004 / {
0005 compatible = "jcore,j2-soc";
0006 model = "J2 FPGA SoC on Mimas v2 board";
0007
0008 #address-cells = <1>;
0009 #size-cells = <1>;
0010
0011 interrupt-parent = <&aic>;
0012
0013 cpus {
0014 #address-cells = <1>;
0015 #size-cells = <0>;
0016
0017 cpu@0 {
0018 device_type = "cpu";
0019 compatible = "jcore,j2";
0020 reg = <0>;
0021 clock-frequency = <50000000>;
0022 d-cache-size = <8192>;
0023 i-cache-size = <8192>;
0024 d-cache-block-size = <16>;
0025 i-cache-block-size = <16>;
0026 };
0027 };
0028
0029 memory@10000000 {
0030 device_type = "memory";
0031 reg = <0x10000000 0x4000000>;
0032 };
0033
0034 aliases {
0035 serial0 = &uart0;
0036 spi0 = &spi0;
0037 };
0038
0039 chosen {
0040 stdout-path = "serial0";
0041 };
0042
0043 soc@abcd0000 {
0044 compatible = "simple-bus";
0045 ranges = <0 0xabcd0000 0x100000>;
0046
0047 #address-cells = <1>;
0048 #size-cells = <1>;
0049
0050 aic: interrupt-controller@200 {
0051 compatible = "jcore,aic1";
0052 reg = <0x200 0x10>;
0053 interrupt-controller;
0054 #interrupt-cells = <1>;
0055 };
0056
0057 cache-controller@c0 {
0058 compatible = "jcore,cache";
0059 reg = <0xc0 4>;
0060 };
0061
0062 timer@200 {
0063 compatible = "jcore,pit";
0064 reg = <0x200 0x30>;
0065 interrupts = <0x48>;
0066 };
0067
0068 spi0: spi@40 {
0069 compatible = "jcore,spi2";
0070
0071 #address-cells = <1>;
0072 #size-cells = <0>;
0073
0074 spi-max-frequency = <25000000>;
0075
0076 reg = <0x40 0x8>;
0077
0078 sdcard@0 {
0079 compatible = "mmc-spi-slot";
0080 reg = <0>;
0081 spi-max-frequency = <25000000>;
0082 voltage-ranges = <3200 3400>;
0083 mode = <0>;
0084 };
0085 };
0086
0087 uart0: serial@100 {
0088 clock-frequency = <125000000>;
0089 compatible = "xlnx,xps-uartlite-1.00.a";
0090 current-speed = <19200>;
0091 xlnx,use-parity = <0>;
0092 xlnx,data-bits = <8>;
0093 device_type = "serial";
0094 interrupts = <0x12>;
0095 port-number = <0>;
0096 reg = <0x100 0x10>;
0097 };
0098 };
0099 };
