0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003 * MPC8555-based STx GP3 Device Tree Source
0004 *
0005 * Copyright 2006, 2008 Freescale Semiconductor Inc.
0006 *
0007 * Copyright 2010 Silicon Turnkey Express LLC.
0008 */
0009
0010 /dts-v1/;
0011
0012 / {
0013 model = "stx,gp3";
0014 compatible = "stx,gp3-8560", "stx,gp3";
0015 #address-cells = <1>;
0016 #size-cells = <1>;
0017
0018 aliases {
0019 ethernet0 = &enet0;
0020 ethernet1 = &enet1;
0021 serial0 = &serial0;
0022 serial1 = &serial1;
0023 pci0 = &pci0;
0024 };
0025
0026 cpus {
0027 #address-cells = <1>;
0028 #size-cells = <0>;
0029
0030 PowerPC,8555@0 {
0031 device_type = "cpu";
0032 reg = <0x0>;
0033 d-cache-line-size = <32>; // 32 bytes
0034 i-cache-line-size = <32>; // 32 bytes
0035 d-cache-size = <0x8000>; // L1, 32K
0036 i-cache-size = <0x8000>; // L1, 32K
0037 timebase-frequency = <0>; // 33 MHz, from uboot
0038 bus-frequency = <0>; // 166 MHz
0039 clock-frequency = <0>; // 825 MHz, from uboot
0040 next-level-cache = <&L2>;
0041 };
0042 };
0043
0044 memory {
0045 device_type = "memory";
0046 reg = <0x00000000 0x10000000>;
0047 };
0048
0049 soc8555@e0000000 {
0050 #address-cells = <1>;
0051 #size-cells = <1>;
0052 device_type = "soc";
0053 compatible = "simple-bus";
0054 ranges = <0x0 0xe0000000 0x100000>;
0055 bus-frequency = <0>;
0056
0057 ecm-law@0 {
0058 compatible = "fsl,ecm-law";
0059 reg = <0x0 0x1000>;
0060 fsl,num-laws = <8>;
0061 };
0062
0063 ecm@1000 {
0064 compatible = "fsl,mpc8555-ecm", "fsl,ecm";
0065 reg = <0x1000 0x1000>;
0066 interrupts = <17 2>;
0067 interrupt-parent = <&mpic>;
0068 };
0069
0070 memory-controller@2000 {
0071 compatible = "fsl,mpc8555-memory-controller";
0072 reg = <0x2000 0x1000>;
0073 interrupt-parent = <&mpic>;
0074 interrupts = <18 2>;
0075 };
0076
0077 L2: l2-cache-controller@20000 {
0078 compatible = "fsl,mpc8555-l2-cache-controller";
0079 reg = <0x20000 0x1000>;
0080 cache-line-size = <32>; // 32 bytes
0081 cache-size = <0x40000>; // L2, 256K
0082 interrupt-parent = <&mpic>;
0083 interrupts = <16 2>;
0084 };
0085
0086 i2c@3000 {
0087 #address-cells = <1>;
0088 #size-cells = <0>;
0089 cell-index = <0>;
0090 compatible = "fsl-i2c";
0091 reg = <0x3000 0x100>;
0092 interrupts = <43 2>;
0093 interrupt-parent = <&mpic>;
0094 dfsrr;
0095 };
0096
0097 dma@21300 {
0098 #address-cells = <1>;
0099 #size-cells = <1>;
0100 compatible = "fsl,mpc8555-dma", "fsl,eloplus-dma";
0101 reg = <0x21300 0x4>;
0102 ranges = <0x0 0x21100 0x200>;
0103 cell-index = <0>;
0104 dma-channel@0 {
0105 compatible = "fsl,mpc8555-dma-channel",
0106 "fsl,eloplus-dma-channel";
0107 reg = <0x0 0x80>;
0108 cell-index = <0>;
0109 interrupt-parent = <&mpic>;
0110 interrupts = <20 2>;
0111 };
0112 dma-channel@80 {
0113 compatible = "fsl,mpc8555-dma-channel",
0114 "fsl,eloplus-dma-channel";
0115 reg = <0x80 0x80>;
0116 cell-index = <1>;
0117 interrupt-parent = <&mpic>;
0118 interrupts = <21 2>;
0119 };
0120 dma-channel@100 {
0121 compatible = "fsl,mpc8555-dma-channel",
0122 "fsl,eloplus-dma-channel";
0123 reg = <0x100 0x80>;
0124 cell-index = <2>;
0125 interrupt-parent = <&mpic>;
0126 interrupts = <22 2>;
0127 };
0128 dma-channel@180 {
0129 compatible = "fsl,mpc8555-dma-channel",
0130 "fsl,eloplus-dma-channel";
0131 reg = <0x180 0x80>;
0132 cell-index = <3>;
0133 interrupt-parent = <&mpic>;
0134 interrupts = <23 2>;
0135 };
0136 };
0137
0138 enet0: ethernet@24000 {
0139 #address-cells = <1>;
0140 #size-cells = <1>;
0141 cell-index = <0>;
0142 device_type = "network";
0143 model = "TSEC";
0144 compatible = "gianfar";
0145 reg = <0x24000 0x1000>;
0146 ranges = <0x0 0x24000 0x1000>;
0147 local-mac-address = [ 00 00 00 00 00 00 ];
0148 interrupts = <29 2 30 2 34 2>;
0149 interrupt-parent = <&mpic>;
0150 tbi-handle = <&tbi0>;
0151 phy-handle = <&phy0>;
0152
0153 mdio@520 {
0154 #address-cells = <1>;
0155 #size-cells = <0>;
0156 compatible = "fsl,gianfar-mdio";
0157 reg = <0x520 0x20>;
0158
0159 phy0: ethernet-phy@2 {
0160 interrupt-parent = <&mpic>;
0161 interrupts = <5 1>;
0162 reg = <0x2>;
0163 };
0164 phy1: ethernet-phy@4 {
0165 interrupt-parent = <&mpic>;
0166 interrupts = <5 1>;
0167 reg = <0x4>;
0168 };
0169 tbi0: tbi-phy@11 {
0170 reg = <0x11>;
0171 device_type = "tbi-phy";
0172 };
0173 };
0174 };
0175
0176 enet1: ethernet@25000 {
0177 #address-cells = <1>;
0178 #size-cells = <1>;
0179 cell-index = <1>;
0180 device_type = "network";
0181 model = "TSEC";
0182 compatible = "gianfar";
0183 reg = <0x25000 0x1000>;
0184 ranges = <0x0 0x25000 0x1000>;
0185 local-mac-address = [ 00 00 00 00 00 00 ];
0186 interrupts = <35 2 36 2 40 2>;
0187 interrupt-parent = <&mpic>;
0188 tbi-handle = <&tbi1>;
0189 phy-handle = <&phy1>;
0190
0191 mdio@520 {
0192 #address-cells = <1>;
0193 #size-cells = <0>;
0194 compatible = "fsl,gianfar-tbi";
0195 reg = <0x520 0x20>;
0196
0197 tbi1: tbi-phy@11 {
0198 reg = <0x11>;
0199 device_type = "tbi-phy";
0200 };
0201 };
0202 };
0203
0204 serial0: serial@4500 {
0205 cell-index = <0>;
0206 device_type = "serial";
0207 compatible = "fsl,ns16550", "ns16550";
0208 reg = <0x4500 0x100>; // reg base, size
0209 clock-frequency = <0>; // should we fill in in uboot?
0210 interrupts = <42 2>;
0211 interrupt-parent = <&mpic>;
0212 };
0213
0214 serial1: serial@4600 {
0215 cell-index = <1>;
0216 device_type = "serial";
0217 compatible = "fsl,ns16550", "ns16550";
0218 reg = <0x4600 0x100>; // reg base, size
0219 clock-frequency = <0>; // should we fill in in uboot?
0220 interrupts = <42 2>;
0221 interrupt-parent = <&mpic>;
0222 };
0223
0224 crypto@30000 {
0225 compatible = "fsl,sec2.0";
0226 reg = <0x30000 0x10000>;
0227 interrupts = <45 2>;
0228 interrupt-parent = <&mpic>;
0229 fsl,num-channels = <4>;
0230 fsl,channel-fifo-len = <24>;
0231 fsl,exec-units-mask = <0x7e>;
0232 fsl,descriptor-types-mask = <0x01010ebf>;
0233 };
0234
0235 mpic: pic@40000 {
0236 interrupt-controller;
0237 #address-cells = <0>;
0238 #interrupt-cells = <2>;
0239 reg = <0x40000 0x40000>;
0240 compatible = "chrp,open-pic";
0241 device_type = "open-pic";
0242 };
0243
0244 cpm@919c0 {
0245 #address-cells = <1>;
0246 #size-cells = <1>;
0247 compatible = "fsl,mpc8555-cpm", "fsl,cpm2";
0248 reg = <0x919c0 0x30>;
0249 ranges;
0250
0251 muram@80000 {
0252 #address-cells = <1>;
0253 #size-cells = <1>;
0254 ranges = <0x0 0x80000 0x10000>;
0255
0256 data@0 {
0257 compatible = "fsl,cpm-muram-data";
0258 reg = <0x0 0x2000 0x9000 0x1000>;
0259 };
0260 };
0261
0262 brg@919f0 {
0263 compatible = "fsl,mpc8555-brg",
0264 "fsl,cpm2-brg",
0265 "fsl,cpm-brg";
0266 reg = <0x919f0 0x10 0x915f0 0x10>;
0267 };
0268
0269 cpmpic: pic@90c00 {
0270 interrupt-controller;
0271 #address-cells = <0>;
0272 #interrupt-cells = <2>;
0273 interrupts = <46 2>;
0274 interrupt-parent = <&mpic>;
0275 reg = <0x90c00 0x80>;
0276 compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic";
0277 };
0278 };
0279 };
0280
0281 pci0: pci@e0008000 {
0282 interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
0283 interrupt-map = <
0284
0285 /* IDSEL 0x10 */
0286 0x8000 0x0 0x0 0x1 &mpic 0x0 0x1
0287 0x8000 0x0 0x0 0x2 &mpic 0x1 0x1
0288 0x8000 0x0 0x0 0x3 &mpic 0x2 0x1
0289 0x8000 0x0 0x0 0x4 &mpic 0x3 0x1
0290
0291 /* IDSEL 0x11 */
0292 0x8800 0x0 0x0 0x1 &mpic 0x0 0x1
0293 0x8800 0x0 0x0 0x2 &mpic 0x1 0x1
0294 0x8800 0x0 0x0 0x3 &mpic 0x2 0x1
0295 0x8800 0x0 0x0 0x4 &mpic 0x3 0x1
0296
0297 /* IDSEL 0x12 (Slot 1) */
0298 0x9000 0x0 0x0 0x1 &mpic 0x0 0x1
0299 0x9000 0x0 0x0 0x2 &mpic 0x1 0x1
0300 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
0301 0x9000 0x0 0x0 0x4 &mpic 0x3 0x1
0302
0303 /* IDSEL 0x13 (Slot 2) */
0304 0x9800 0x0 0x0 0x1 &mpic 0x1 0x1
0305 0x9800 0x0 0x0 0x2 &mpic 0x2 0x1
0306 0x9800 0x0 0x0 0x3 &mpic 0x3 0x1
0307 0x9800 0x0 0x0 0x4 &mpic 0x0 0x1
0308
0309 /* IDSEL 0x14 (Slot 3) */
0310 0xa000 0x0 0x0 0x1 &mpic 0x2 0x1
0311 0xa000 0x0 0x0 0x2 &mpic 0x3 0x1
0312 0xa000 0x0 0x0 0x3 &mpic 0x0 0x1
0313 0xa000 0x0 0x0 0x4 &mpic 0x1 0x1
0314
0315 /* IDSEL 0x15 (Slot 4) */
0316 0xa800 0x0 0x0 0x1 &mpic 0x3 0x1
0317 0xa800 0x0 0x0 0x2 &mpic 0x0 0x1
0318 0xa800 0x0 0x0 0x3 &mpic 0x1 0x1
0319 0xa800 0x0 0x0 0x4 &mpic 0x2 0x1
0320
0321 /* Bus 1 (Tundra Bridge) */
0322 /* IDSEL 0x12 (ISA bridge) */
0323 0x19000 0x0 0x0 0x1 &mpic 0x0 0x1
0324 0x19000 0x0 0x0 0x2 &mpic 0x1 0x1
0325 0x19000 0x0 0x0 0x3 &mpic 0x2 0x1
0326 0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>;
0327 interrupt-parent = <&mpic>;
0328 interrupts = <24 2>;
0329 bus-range = <0 0>;
0330 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
0331 0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
0332 clock-frequency = <66666666>;
0333 #interrupt-cells = <1>;
0334 #size-cells = <2>;
0335 #address-cells = <3>;
0336 reg = <0xe0008000 0x1000>;
0337 compatible = "fsl,mpc8540-pci";
0338 device_type = "pci";
0339
0340 i8259@19000 {
0341 interrupt-controller;
0342 device_type = "interrupt-controller";
0343 reg = <0x19000 0x0 0x0 0x0 0x1>;
0344 #address-cells = <0>;
0345 #interrupt-cells = <2>;
0346 compatible = "chrp,iic";
0347 interrupts = <1>;
0348 interrupt-parent = <&pci0>;
0349 };
0350 };
0351
0352 pci1: pci@e0009000 {
0353 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
0354 interrupt-map = <
0355
0356 /* IDSEL 0x15 */
0357 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
0358 0xa800 0x0 0x0 0x2 &mpic 0xb 0x1
0359 0xa800 0x0 0x0 0x3 &mpic 0xb 0x1
0360 0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>;
0361 interrupt-parent = <&mpic>;
0362 interrupts = <25 2>;
0363 bus-range = <0 0>;
0364 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
0365 0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
0366 clock-frequency = <66666666>;
0367 #interrupt-cells = <1>;
0368 #size-cells = <2>;
0369 #address-cells = <3>;
0370 reg = <0xe0009000 0x1000>;
0371 compatible = "fsl,mpc8540-pci";
0372 device_type = "pci";
0373 };
0374 };
