0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003 * MPC8313E RDB Device Tree Source
0004 *
0005 * Copyright 2005, 2006, 2007 Freescale Semiconductor Inc.
0006 */
0007
0008 /dts-v1/;
0009
0010 / {
0011 model = "MPC8313ERDB";
0012 compatible = "MPC8313ERDB", "MPC831xRDB", "MPC83xxRDB";
0013 #address-cells = <1>;
0014 #size-cells = <1>;
0015
0016 aliases {
0017 ethernet0 = &enet0;
0018 ethernet1 = &enet1;
0019 serial0 = &serial0;
0020 serial1 = &serial1;
0021 pci0 = &pci0;
0022 };
0023
0024 cpus {
0025 #address-cells = <1>;
0026 #size-cells = <0>;
0027
0028 PowerPC,8313@0 {
0029 device_type = "cpu";
0030 reg = <0x0>;
0031 d-cache-line-size = <32>;
0032 i-cache-line-size = <32>;
0033 d-cache-size = <16384>;
0034 i-cache-size = <16384>;
0035 timebase-frequency = <0>; // from bootloader
0036 bus-frequency = <0>; // from bootloader
0037 clock-frequency = <0>; // from bootloader
0038 };
0039 };
0040
0041 memory {
0042 device_type = "memory";
0043 reg = <0x00000000 0x08000000>; // 128MB at 0
0044 };
0045
0046 localbus@e0005000 {
0047 #address-cells = <2>;
0048 #size-cells = <1>;
0049 compatible = "fsl,mpc8313-elbc", "fsl,elbc", "simple-bus";
0050 reg = <0xe0005000 0x1000>;
0051 interrupts = <77 0x8>;
0052 interrupt-parent = <&ipic>;
0053
0054 // CS0 and CS1 are swapped when
0055 // booting from nand, but the
0056 // addresses are the same.
0057 ranges = <0x0 0x0 0xfe000000 0x00800000
0058 0x1 0x0 0xe2800000 0x00008000
0059 0x2 0x0 0xf0000000 0x00020000
0060 0x3 0x0 0xfa000000 0x00008000>;
0061
0062 flash@0,0 {
0063 #address-cells = <1>;
0064 #size-cells = <1>;
0065 compatible = "cfi-flash";
0066 reg = <0x0 0x0 0x800000>;
0067 bank-width = <2>;
0068 device-width = <1>;
0069 };
0070
0071 nand@1,0 {
0072 #address-cells = <1>;
0073 #size-cells = <1>;
0074 compatible = "fsl,mpc8313-fcm-nand",
0075 "fsl,elbc-fcm-nand";
0076 reg = <0x1 0x0 0x2000>;
0077
0078 u-boot@0 {
0079 reg = <0x0 0x100000>;
0080 read-only;
0081 };
0082
0083 kernel@100000 {
0084 reg = <0x100000 0x300000>;
0085 };
0086
0087 fs@400000 {
0088 reg = <0x400000 0x1c00000>;
0089 };
0090 };
0091 };
0092
0093 soc8313@e0000000 {
0094 #address-cells = <1>;
0095 #size-cells = <1>;
0096 device_type = "soc";
0097 compatible = "simple-bus";
0098 ranges = <0x0 0xe0000000 0x00100000>;
0099 reg = <0xe0000000 0x00000200>;
0100 bus-frequency = <0>;
0101
0102 wdt@200 {
0103 device_type = "watchdog";
0104 compatible = "mpc83xx_wdt";
0105 reg = <0x200 0x100>;
0106 };
0107
0108 sleep-nexus {
0109 #address-cells = <1>;
0110 #size-cells = <1>;
0111 compatible = "simple-bus";
0112 sleep = <&pmc 0x03000000>;
0113 ranges;
0114
0115 i2c@3000 {
0116 #address-cells = <1>;
0117 #size-cells = <0>;
0118 cell-index = <0>;
0119 compatible = "fsl-i2c";
0120 reg = <0x3000 0x100>;
0121 interrupts = <14 0x8>;
0122 interrupt-parent = <&ipic>;
0123 dfsrr;
0124 rtc@68 {
0125 compatible = "dallas,ds1339";
0126 reg = <0x68>;
0127 };
0128 };
0129
0130 crypto@30000 {
0131 compatible = "fsl,sec2.2", "fsl,sec2.1",
0132 "fsl,sec2.0";
0133 reg = <0x30000 0x10000>;
0134 interrupts = <11 0x8>;
0135 interrupt-parent = <&ipic>;
0136 fsl,num-channels = <1>;
0137 fsl,channel-fifo-len = <24>;
0138 fsl,exec-units-mask = <0x4c>;
0139 fsl,descriptor-types-mask = <0x0122003f>;
0140 };
0141 };
0142
0143 i2c@3100 {
0144 #address-cells = <1>;
0145 #size-cells = <0>;
0146 cell-index = <1>;
0147 compatible = "fsl-i2c";
0148 reg = <0x3100 0x100>;
0149 interrupts = <15 0x8>;
0150 interrupt-parent = <&ipic>;
0151 dfsrr;
0152 };
0153
0154 spi@7000 {
0155 cell-index = <0>;
0156 compatible = "fsl,spi";
0157 reg = <0x7000 0x1000>;
0158 interrupts = <16 0x8>;
0159 interrupt-parent = <&ipic>;
0160 mode = "cpu";
0161 };
0162
0163 /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
0164 usb@23000 {
0165 compatible = "fsl-usb2-dr";
0166 reg = <0x23000 0x1000>;
0167 #address-cells = <1>;
0168 #size-cells = <0>;
0169 interrupt-parent = <&ipic>;
0170 interrupts = <38 0x8>;
0171 phy_type = "utmi_wide";
0172 sleep = <&pmc 0x00300000>;
0173 };
0174
0175 ptp_clock@24E00 {
0176 compatible = "fsl,etsec-ptp";
0177 reg = <0x24E00 0xB0>;
0178 interrupts = <12 0x8 13 0x8>;
0179 interrupt-parent = < &ipic >;
0180 fsl,tclk-period = <10>;
0181 fsl,tmr-prsc = <100>;
0182 fsl,tmr-add = <0x999999A4>;
0183 fsl,tmr-fiper1 = <0x3B9AC9F6>;
0184 fsl,tmr-fiper2 = <0x00018696>;
0185 fsl,max-adj = <659999998>;
0186 };
0187
0188 enet0: ethernet@24000 {
0189 #address-cells = <1>;
0190 #size-cells = <1>;
0191 sleep = <&pmc 0x20000000>;
0192 ranges = <0x0 0x24000 0x1000>;
0193
0194 cell-index = <0>;
0195 device_type = "network";
0196 model = "eTSEC";
0197 compatible = "gianfar";
0198 reg = <0x24000 0x1000>;
0199 local-mac-address = [ 00 00 00 00 00 00 ];
0200 interrupts = <37 0x8 36 0x8 35 0x8>;
0201 interrupt-parent = <&ipic>;
0202 tbi-handle = < &tbi0 >;
0203 /* Vitesse 7385 isn't on the MDIO bus */
0204 fixed-link = <1 1 1000 0 0>;
0205 fsl,magic-packet;
0206
0207 mdio@520 {
0208 #address-cells = <1>;
0209 #size-cells = <0>;
0210 compatible = "fsl,gianfar-mdio";
0211 reg = <0x520 0x20>;
0212 phy4: ethernet-phy@4 {
0213 interrupt-parent = <&ipic>;
0214 interrupts = <20 0x8>;
0215 reg = <0x4>;
0216 };
0217 tbi0: tbi-phy@11 {
0218 reg = <0x11>;
0219 device_type = "tbi-phy";
0220 };
0221 };
0222 };
0223
0224 enet1: ethernet@25000 {
0225 #address-cells = <1>;
0226 #size-cells = <1>;
0227 cell-index = <1>;
0228 device_type = "network";
0229 model = "eTSEC";
0230 compatible = "gianfar";
0231 reg = <0x25000 0x1000>;
0232 ranges = <0x0 0x25000 0x1000>;
0233 local-mac-address = [ 00 00 00 00 00 00 ];
0234 interrupts = <34 0x8 33 0x8 32 0x8>;
0235 interrupt-parent = <&ipic>;
0236 tbi-handle = < &tbi1 >;
0237 phy-handle = < &phy4 >;
0238 sleep = <&pmc 0x10000000>;
0239 fsl,magic-packet;
0240
0241 mdio@520 {
0242 #address-cells = <1>;
0243 #size-cells = <0>;
0244 compatible = "fsl,gianfar-tbi";
0245 reg = <0x520 0x20>;
0246
0247 tbi1: tbi-phy@11 {
0248 reg = <0x11>;
0249 device_type = "tbi-phy";
0250 };
0251 };
0252
0253
0254 };
0255
0256 serial0: serial@4500 {
0257 cell-index = <0>;
0258 device_type = "serial";
0259 compatible = "fsl,ns16550", "ns16550";
0260 reg = <0x4500 0x100>;
0261 clock-frequency = <0>;
0262 interrupts = <9 0x8>;
0263 interrupt-parent = <&ipic>;
0264 };
0265
0266 serial1: serial@4600 {
0267 cell-index = <1>;
0268 device_type = "serial";
0269 compatible = "fsl,ns16550", "ns16550";
0270 reg = <0x4600 0x100>;
0271 clock-frequency = <0>;
0272 interrupts = <10 0x8>;
0273 interrupt-parent = <&ipic>;
0274 };
0275
0276 /* IPIC
0277 * interrupts cell = <intr #, sense>
0278 * sense values match linux IORESOURCE_IRQ_* defines:
0279 * sense == 8: Level, low assertion
0280 * sense == 2: Edge, high-to-low change
0281 */
0282 ipic: pic@700 {
0283 interrupt-controller;
0284 #address-cells = <0>;
0285 #interrupt-cells = <2>;
0286 reg = <0x700 0x100>;
0287 device_type = "ipic";
0288 };
0289
0290 pmc: power@b00 {
0291 compatible = "fsl,mpc8313-pmc", "fsl,mpc8349-pmc";
0292 reg = <0xb00 0x100 0xa00 0x100>;
0293 interrupts = <80 8>;
0294 interrupt-parent = <&ipic>;
0295 fsl,mpc8313-wakeup-timer = <>m1>;
0296
0297 /* Remove this (or change to "okay") if you have
0298 * a REVA3 or later board, if you apply one of the
0299 * workarounds listed in section 8.5 of the board
0300 * manual, or if you are adapting this device tree
0301 * to a different board.
0302 */
0303 status = "fail";
0304 };
0305
0306 gtm1: timer@500 {
0307 compatible = "fsl,mpc8313-gtm", "fsl,gtm";
0308 reg = <0x500 0x100>;
0309 interrupts = <90 8 78 8 84 8 72 8>;
0310 interrupt-parent = <&ipic>;
0311 };
0312
0313 timer@600 {
0314 compatible = "fsl,mpc8313-gtm", "fsl,gtm";
0315 reg = <0x600 0x100>;
0316 interrupts = <91 8 79 8 85 8 73 8>;
0317 interrupt-parent = <&ipic>;
0318 };
0319 };
0320
0321 sleep-nexus {
0322 #address-cells = <1>;
0323 #size-cells = <1>;
0324 compatible = "simple-bus";
0325 sleep = <&pmc 0x00010000>;
0326 ranges;
0327
0328 pci0: pci@e0008500 {
0329 cell-index = <1>;
0330 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
0331 interrupt-map = <
0332 /* IDSEL 0x0E -mini PCI */
0333 0x7000 0x0 0x0 0x1 &ipic 18 0x8
0334 0x7000 0x0 0x0 0x2 &ipic 18 0x8
0335 0x7000 0x0 0x0 0x3 &ipic 18 0x8
0336 0x7000 0x0 0x0 0x4 &ipic 18 0x8
0337
0338 /* IDSEL 0x0F - PCI slot */
0339 0x7800 0x0 0x0 0x1 &ipic 17 0x8
0340 0x7800 0x0 0x0 0x2 &ipic 18 0x8
0341 0x7800 0x0 0x0 0x3 &ipic 17 0x8
0342 0x7800 0x0 0x0 0x4 &ipic 18 0x8>;
0343 interrupt-parent = <&ipic>;
0344 interrupts = <66 0x8>;
0345 bus-range = <0x0 0x0>;
0346 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
0347 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
0348 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
0349 clock-frequency = <66666666>;
0350 #interrupt-cells = <1>;
0351 #size-cells = <2>;
0352 #address-cells = <3>;
0353 reg = <0xe0008500 0x100 /* internal registers */
0354 0xe0008300 0x8>; /* config space access registers */
0355 compatible = "fsl,mpc8349-pci";
0356 device_type = "pci";
0357 };
0358
0359 dma@82a8 {
0360 #address-cells = <1>;
0361 #size-cells = <1>;
0362 compatible = "fsl,mpc8313-dma", "fsl,elo-dma";
0363 reg = <0xe00082a8 4>;
0364 ranges = <0 0xe0008100 0x1a8>;
0365 interrupt-parent = <&ipic>;
0366 interrupts = <71 8>;
0367
0368 dma-channel@0 {
0369 compatible = "fsl,mpc8313-dma-channel",
0370 "fsl,elo-dma-channel";
0371 reg = <0 0x28>;
0372 interrupt-parent = <&ipic>;
0373 interrupts = <71 8>;
0374 cell-index = <0>;
0375 };
0376
0377 dma-channel@80 {
0378 compatible = "fsl,mpc8313-dma-channel",
0379 "fsl,elo-dma-channel";
0380 reg = <0x80 0x28>;
0381 interrupt-parent = <&ipic>;
0382 interrupts = <71 8>;
0383 cell-index = <1>;
0384 };
0385
0386 dma-channel@100 {
0387 compatible = "fsl,mpc8313-dma-channel",
0388 "fsl,elo-dma-channel";
0389 reg = <0x100 0x28>;
0390 interrupt-parent = <&ipic>;
0391 interrupts = <71 8>;
0392 cell-index = <2>;
0393 };
0394
0395 dma-channel@180 {
0396 compatible = "fsl,mpc8313-dma-channel",
0397 "fsl,elo-dma-channel";
0398 reg = <0x180 0x28>;
0399 interrupt-parent = <&ipic>;
0400 interrupts = <71 8>;
0401 cell-index = <3>;
0402 };
0403 };
0404 };
0405 };
