0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003 * charon board Device Tree Source
0004 *
0005 * Copyright (C) 2007 Semihalf
0006 * Marian Balakowicz <m8@semihalf.com>
0007 *
0008 * Copyright (C) 2010 DENX Software Engineering GmbH
0009 * Heiko Schocher <hs@denx.de>
0010 */
0011
0012 /dts-v1/;
0013
0014 / {
0015 model = "anon,charon";
0016 compatible = "anon,charon";
0017 #address-cells = <1>;
0018 #size-cells = <1>;
0019 interrupt-parent = <&mpc5200_pic>;
0020
0021 cpus {
0022 #address-cells = <1>;
0023 #size-cells = <0>;
0024
0025 PowerPC,5200@0 {
0026 device_type = "cpu";
0027 reg = <0>;
0028 d-cache-line-size = <32>;
0029 i-cache-line-size = <32>;
0030 d-cache-size = <0x4000>; // L1, 16K
0031 i-cache-size = <0x4000>; // L1, 16K
0032 timebase-frequency = <0>; // from bootloader
0033 bus-frequency = <0>; // from bootloader
0034 clock-frequency = <0>; // from bootloader
0035 };
0036 };
0037
0038 memory@0 {
0039 device_type = "memory";
0040 reg = <0x00000000 0x08000000>; // 128MB
0041 };
0042
0043 soc5200@f0000000 {
0044 #address-cells = <1>;
0045 #size-cells = <1>;
0046 compatible = "fsl,mpc5200-immr";
0047 ranges = <0 0xf0000000 0x0000c000>;
0048 reg = <0xf0000000 0x00000100>;
0049 bus-frequency = <0>; // from bootloader
0050 system-frequency = <0>; // from bootloader
0051
0052 cdm@200 {
0053 compatible = "fsl,mpc5200-cdm";
0054 reg = <0x200 0x38>;
0055 };
0056
0057 mpc5200_pic: interrupt-controller@500 {
0058 // 5200 interrupts are encoded into two levels;
0059 interrupt-controller;
0060 #interrupt-cells = <3>;
0061 compatible = "fsl,mpc5200-pic";
0062 reg = <0x500 0x80>;
0063 };
0064
0065 timer@600 { // General Purpose Timer
0066 compatible = "fsl,mpc5200-gpt";
0067 reg = <0x600 0x10>;
0068 interrupts = <1 9 0>;
0069 fsl,has-wdt;
0070 };
0071
0072 can@900 {
0073 compatible = "fsl,mpc5200-mscan";
0074 interrupts = <2 17 0>;
0075 reg = <0x900 0x80>;
0076 };
0077
0078 can@980 {
0079 compatible = "fsl,mpc5200-mscan";
0080 interrupts = <2 18 0>;
0081 reg = <0x980 0x80>;
0082 };
0083
0084 gpio_simple: gpio@b00 {
0085 compatible = "fsl,mpc5200-gpio";
0086 reg = <0xb00 0x40>;
0087 interrupts = <1 7 0>;
0088 gpio-controller;
0089 #gpio-cells = <2>;
0090 };
0091
0092 usb@1000 {
0093 compatible = "fsl,mpc5200-ohci","ohci-be";
0094 reg = <0x1000 0xff>;
0095 interrupts = <2 6 0>;
0096 };
0097
0098 dma-controller@1200 {
0099 device_type = "dma-controller";
0100 compatible = "fsl,mpc5200-bestcomm";
0101 reg = <0x1200 0x80>;
0102 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
0103 3 4 0 3 5 0 3 6 0 3 7 0
0104 3 8 0 3 9 0 3 10 0 3 11 0
0105 3 12 0 3 13 0 3 14 0 3 15 0>;
0106 };
0107
0108 xlb@1f00 {
0109 compatible = "fsl,mpc5200-xlb";
0110 reg = <0x1f00 0x100>;
0111 };
0112
0113 serial@2000 { // PSC1
0114 compatible = "fsl,mpc5200-psc-uart";
0115 reg = <0x2000 0x100>;
0116 interrupts = <2 1 0>;
0117 };
0118
0119 serial@2400 { // PSC3
0120 compatible = "fsl,mpc5200-psc-uart";
0121 reg = <0x2400 0x100>;
0122 interrupts = <2 3 0>;
0123 };
0124
0125 ethernet@3000 {
0126 compatible = "fsl,mpc5200-fec";
0127 reg = <0x3000 0x400>;
0128 local-mac-address = [ 00 00 00 00 00 00 ];
0129 interrupts = <2 5 0>;
0130 fixed-link = <1 1 100 0 0>;
0131 };
0132
0133 mdio@3000 {
0134 #address-cells = <1>;
0135 #size-cells = <0>;
0136 compatible = "fsl,mpc5200-mdio";
0137 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
0138 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
0139 };
0140
0141 ata@3a00 {
0142 compatible = "fsl,mpc5200-ata";
0143 reg = <0x3a00 0x100>;
0144 interrupts = <2 7 0>;
0145 };
0146
0147 i2c@3d00 {
0148 #address-cells = <1>;
0149 #size-cells = <0>;
0150 compatible = "fsl,mpc5200-i2c","fsl-i2c";
0151 reg = <0x3d00 0x40>;
0152 interrupts = <2 15 0>;
0153 };
0154
0155
0156 i2c@3d40 {
0157 #address-cells = <1>;
0158 #size-cells = <0>;
0159 compatible = "fsl,mpc5200-i2c","fsl-i2c";
0160 reg = <0x3d40 0x40>;
0161 interrupts = <2 16 0>;
0162
0163 dtt@28 {
0164 compatible = "national,lm80";
0165 reg = <0x28>;
0166 };
0167
0168 rtc@68 {
0169 compatible = "dallas,ds1374";
0170 reg = <0x68>;
0171 };
0172 };
0173
0174 sram@8000 {
0175 compatible = "fsl,mpc5200-sram";
0176 reg = <0x8000 0x4000>;
0177 };
0178 };
0179
0180 localbus {
0181 compatible = "fsl,mpc5200-lpb","simple-bus";
0182 #address-cells = <2>;
0183 #size-cells = <1>;
0184 ranges = < 0 0 0xfc000000 0x02000000
0185 1 0 0xe0000000 0x04000000 // CS1 range, SM501
0186 3 0 0xe8000000 0x00080000>;
0187
0188 flash@0,0 {
0189 compatible = "cfi-flash";
0190 reg = <0 0 0x02000000>;
0191 bank-width = <4>;
0192 device-width = <2>;
0193 #size-cells = <1>;
0194 #address-cells = <1>;
0195 };
0196
0197 display@1,0 {
0198 compatible = "smi,sm501";
0199 reg = <1 0x00000000 0x00800000
0200 1 0x03e00000 0x00200000>;
0201 mode = "640x480-32@60";
0202 interrupts = <1 1 3>;
0203 little-endian;
0204 };
0205
0206 mram0@3,0 {
0207 compatible = "mtd-ram";
0208 reg = <3 0x00000 0x80000>;
0209 bank-width = <1>;
0210 };
0211 };
0212
0213 pci@f0000d00 {
0214 #interrupt-cells = <1>;
0215 #size-cells = <2>;
0216 #address-cells = <3>;
0217 device_type = "pci";
0218 compatible = "fsl,mpc5200-pci";
0219 reg = <0xf0000d00 0x100>;
0220 interrupt-map-mask = <0xf800 0 0 7>;
0221 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3
0222 0xc000 0 0 2 &mpc5200_pic 0 0 3
0223 0xc000 0 0 3 &mpc5200_pic 0 0 3
0224 0xc000 0 0 4 &mpc5200_pic 0 0 3>;
0225 clock-frequency = <0>; // From boot loader
0226 interrupts = <2 8 0 2 9 0 2 10 0>;
0227 bus-range = <0 0>;
0228 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000>,
0229 <0x02000000 0 0x90000000 0x90000000 0 0x10000000>,
0230 <0x01000000 0 0x00000000 0xa0000000 0 0x01000000>;
0231 };
0232 };
