0001 /dts-v1/;
0002 / {
0003 compatible = "opencores,or1ksim";
0004 #address-cells = <1>;
0005 #size-cells = <1>;
0006 interrupt-parent = <&pic>;
0007
0008 aliases {
0009 uart0 = &serial0;
0010 };
0011
0012 chosen {
0013 bootargs = "earlycon";
0014 stdout-path = "uart0:115200";
0015 };
0016
0017 memory@0 {
0018 device_type = "memory";
0019 reg = <0x00000000 0x02000000>;
0020 };
0021
0022 cpus {
0023 #address-cells = <1>;
0024 #size-cells = <0>;
0025 cpu@0 {
0026 compatible = "opencores,or1200-rtlsvn481";
0027 reg = <0>;
0028 clock-frequency = <20000000>;
0029 };
0030 cpu@1 {
0031 compatible = "opencores,or1200-rtlsvn481";
0032 reg = <1>;
0033 clock-frequency = <20000000>;
0034 };
0035 };
0036
0037 ompic: ompic@98000000 {
0038 compatible = "openrisc,ompic";
0039 reg = <0x98000000 16>;
0040 interrupt-controller;
0041 #interrupt-cells = <0>;
0042 interrupts = <1>;
0043 };
0044
0045 /*
0046 * OR1K PIC is built into CPU and accessed via special purpose
0047 * registers. It is not addressable and, hence, has no 'reg'
0048 * property.
0049 */
0050 pic: pic {
0051 compatible = "opencores,or1k-pic-level";
0052 #interrupt-cells = <1>;
0053 interrupt-controller;
0054 };
0055
0056 serial0: serial@90000000 {
0057 compatible = "opencores,uart16550-rtlsvn105", "ns16550a";
0058 reg = <0x90000000 0x100>;
0059 interrupts = <2>;
0060 clock-frequency = <20000000>;
0061 };
0062
0063 enet0: ethoc@92000000 {
0064 compatible = "opencores,ethoc";
0065 reg = <0x92000000 0x800>;
0066 interrupts = <4>;
0067 big-endian;
0068 };
0069 };
