0001 // SPDX-License-Identifier: GPL-2.0
0002 /dts-v1/;
0003 / {
0004 compatible = "opencores,or1ksim";
0005 #address-cells = <1>;
0006 #size-cells = <1>;
0007 interrupt-parent = <&pic>;
0008
0009 aliases {
0010 uart0 = &serial0;
0011 };
0012
0013 chosen {
0014 bootargs = "earlycon";
0015 stdout-path = "uart0:115200";
0016 };
0017
0018 memory@0 {
0019 device_type = "memory";
0020 reg = <0x00000000 0x02000000>;
0021 };
0022
0023 cpus {
0024 #address-cells = <1>;
0025 #size-cells = <0>;
0026 cpu@0 {
0027 compatible = "opencores,or1200-rtlsvn481";
0028 reg = <0>;
0029 clock-frequency = <20000000>;
0030 };
0031 };
0032
0033 /*
0034 * OR1K PIC is built into CPU and accessed via special purpose
0035 * registers. It is not addressable and, hence, has no 'reg'
0036 * property.
0037 */
0038 pic: pic {
0039 compatible = "opencores,or1k-pic";
0040 #interrupt-cells = <1>;
0041 interrupt-controller;
0042 };
0043
0044 serial0: serial@90000000 {
0045 compatible = "opencores,uart16550-rtlsvn105", "ns16550a";
0046 reg = <0x90000000 0x100>;
0047 interrupts = <2>;
0048 clock-frequency = <20000000>;
0049 };
0050
0051 enet0: ethoc@92000000 {
0052 compatible = "opencores,ethoc";
0053 reg = <0x92000000 0x800>;
0054 interrupts = <4>;
0055 big-endian;
0056 };
0057 };
