0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright (C) 2015 Altera Corporation. All rights reserved.
0004 */
0005
0006 /dts-v1/;
0007
0008 / {
0009 model = "Altera NiosII Max10";
0010 compatible = "altr,niosii-max10";
0011 #address-cells = <1>;
0012 #size-cells = <1>;
0013
0014 cpus {
0015 #address-cells = <1>;
0016 #size-cells = <0>;
0017
0018 cpu: cpu@0 {
0019 device_type = "cpu";
0020 compatible = "altr,nios2-1.1";
0021 reg = <0x00000000>;
0022 interrupt-controller;
0023 #interrupt-cells = <1>;
0024 altr,exception-addr = <0xc8000120>;
0025 altr,fast-tlb-miss-addr = <0xc0000100>;
0026 altr,has-div = <1>;
0027 altr,has-initda = <1>;
0028 altr,has-mmu = <1>;
0029 altr,has-mul = <1>;
0030 altr,implementation = "fast";
0031 altr,pid-num-bits = <8>;
0032 altr,reset-addr = <0xd4000000>;
0033 altr,tlb-num-entries = <256>;
0034 altr,tlb-num-ways = <16>;
0035 altr,tlb-ptr-sz = <8>;
0036 clock-frequency = <75000000>;
0037 dcache-line-size = <32>;
0038 dcache-size = <32768>;
0039 icache-line-size = <32>;
0040 icache-size = <32768>;
0041 };
0042 };
0043
0044 memory {
0045 device_type = "memory";
0046 reg = <0x08000000 0x08000000>,
0047 <0x00000000 0x00000400>;
0048 };
0049
0050 sopc0: sopc@0 {
0051 device_type = "soc";
0052 ranges;
0053 #address-cells = <1>;
0054 #size-cells = <1>;
0055 compatible = "altr,avalon", "simple-bus";
0056 bus-frequency = <75000000>;
0057
0058 jtag_uart: serial@18001530 {
0059 compatible = "altr,juart-1.0";
0060 reg = <0x18001530 0x00000008>;
0061 interrupt-parent = <&cpu>;
0062 interrupts = <7>;
0063 };
0064
0065 a_16550_uart_0: serial@18001600 {
0066 compatible = "altr,16550-FIFO32", "ns16550a";
0067 reg = <0x18001600 0x00000200>;
0068 interrupt-parent = <&cpu>;
0069 interrupts = <1>;
0070 auto-flow-control = <1>;
0071 clock-frequency = <50000000>;
0072 fifo-size = <32>;
0073 reg-io-width = <4>;
0074 reg-shift = <2>;
0075 tx-threshold = <16>;
0076 };
0077
0078 sysid: sysid@18001528 {
0079 compatible = "altr,sysid-1.0";
0080 reg = <0x18001528 0x00000008>;
0081 id = <4207856382>;
0082 timestamp = <1431309290>;
0083 };
0084
0085 rgmii_0_eth_tse_0: ethernet@400 {
0086 compatible = "altr,tse-msgdma-1.0", "altr,tse-1.0";
0087 reg = <0x00000400 0x00000400>,
0088 <0x00000820 0x00000020>,
0089 <0x00000800 0x00000020>,
0090 <0x000008c0 0x00000008>,
0091 <0x00000840 0x00000020>,
0092 <0x00000860 0x00000020>;
0093 reg-names = "control_port", "rx_csr", "rx_desc", "rx_resp", "tx_csr", "tx_desc";
0094 interrupt-parent = <&cpu>;
0095 interrupts = <2 3>;
0096 interrupt-names = "rx_irq", "tx_irq";
0097 rx-fifo-depth = <8192>;
0098 tx-fifo-depth = <8192>;
0099 address-bits = <48>;
0100 max-frame-size = <1518>;
0101 local-mac-address = [00 00 00 00 00 00];
0102 altr,has-supplementary-unicast;
0103 altr,enable-sup-addr = <1>;
0104 altr,has-hash-multicast-filter;
0105 altr,enable-hash = <1>;
0106 phy-mode = "rgmii-id";
0107 phy-handle = <&phy0>;
0108 rgmii_0_eth_tse_0_mdio: mdio {
0109 compatible = "altr,tse-mdio";
0110 #address-cells = <1>;
0111 #size-cells = <0>;
0112 phy0: ethernet-phy@0 {
0113 reg = <0>;
0114 device_type = "ethernet-phy";
0115 };
0116 };
0117 };
0118
0119 enet_pll: clock@0 {
0120 compatible = "altr,pll-1.0";
0121 #clock-cells = <1>;
0122
0123 enet_pll_c0: enet_pll_c0 {
0124 compatible = "fixed-clock";
0125 #clock-cells = <0>;
0126 clock-frequency = <125000000>;
0127 clock-output-names = "enet_pll-c0";
0128 };
0129
0130 enet_pll_c1: enet_pll_c1 {
0131 compatible = "fixed-clock";
0132 #clock-cells = <0>;
0133 clock-frequency = <25000000>;
0134 clock-output-names = "enet_pll-c1";
0135 };
0136
0137 enet_pll_c2: enet_pll_c2 {
0138 compatible = "fixed-clock";
0139 #clock-cells = <0>;
0140 clock-frequency = <2500000>;
0141 clock-output-names = "enet_pll-c2";
0142 };
0143 };
0144
0145 sys_pll: clock@1 {
0146 compatible = "altr,pll-1.0";
0147 #clock-cells = <1>;
0148
0149 sys_pll_c0: sys_pll_c0 {
0150 compatible = "fixed-clock";
0151 #clock-cells = <0>;
0152 clock-frequency = <100000000>;
0153 clock-output-names = "sys_pll-c0";
0154 };
0155
0156 sys_pll_c1: sys_pll_c1 {
0157 compatible = "fixed-clock";
0158 #clock-cells = <0>;
0159 clock-frequency = <50000000>;
0160 clock-output-names = "sys_pll-c1";
0161 };
0162
0163 sys_pll_c2: sys_pll_c2 {
0164 compatible = "fixed-clock";
0165 #clock-cells = <0>;
0166 clock-frequency = <75000000>;
0167 clock-output-names = "sys_pll-c2";
0168 };
0169 };
0170
0171 sys_clk_timer: timer@18001440 {
0172 compatible = "altr,timer-1.0";
0173 reg = <0x18001440 0x00000020>;
0174 interrupt-parent = <&cpu>;
0175 interrupts = <0>;
0176 clock-frequency = <75000000>;
0177 };
0178
0179 led_pio: gpio@180014d0 {
0180 compatible = "altr,pio-1.0";
0181 reg = <0x180014d0 0x00000010>;
0182 altr,ngpio = <4>;
0183 #gpio-cells = <2>;
0184 gpio-controller;
0185 };
0186
0187 button_pio: gpio@180014c0 {
0188 compatible = "altr,pio-1.0";
0189 reg = <0x180014c0 0x00000010>;
0190 interrupt-parent = <&cpu>;
0191 interrupts = <6>;
0192 altr,ngpio = <3>;
0193 altr,interrupt-type = <2>;
0194 edge_type = <1>;
0195 level_trigger = <0>;
0196 #gpio-cells = <2>;
0197 gpio-controller;
0198 };
0199
0200 sys_clk_timer_1: timer@880 {
0201 compatible = "altr,timer-1.0";
0202 reg = <0x00000880 0x00000020>;
0203 interrupt-parent = <&cpu>;
0204 interrupts = <5>;
0205 clock-frequency = <75000000>;
0206 };
0207
0208 fpga_leds: leds {
0209 compatible = "gpio-leds";
0210
0211 led_fpga0: fpga0 {
0212 label = "fpga_led0";
0213 gpios = <&led_pio 0 1>;
0214 };
0215
0216 led_fpga1: fpga1 {
0217 label = "fpga_led1";
0218 gpios = <&led_pio 1 1>;
0219 };
0220
0221 led_fpga2: fpga2 {
0222 label = "fpga_led2";
0223 gpios = <&led_pio 2 1>;
0224 };
0225
0226 led_fpga3: fpga3 {
0227 label = "fpga_led3";
0228 gpios = <&led_pio 3 1>;
0229 };
0230 };
0231 };
0232
0233 chosen {
0234 bootargs = "debug earlycon console=ttyS0,115200";
0235 stdout-path = &a_16550_uart_0;
0236 };
0237 };
