0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003 * Device Tree Generator version: 1.1
0004 *
0005 * (C) Copyright 2007-2008 Xilinx, Inc.
0006 * (C) Copyright 2007-2009 Michal Simek
0007 *
0008 * Michal SIMEK <monstr@monstr.eu>
0009 *
0010 * CAUTION: This file is automatically generated by libgen.
0011 * Version: Xilinx EDK 10.1.03 EDK_K_SP3.6
0012 *
0013 * XPS project directory: Xilinx-ML505-ll_temac-sgdma-MMU-FDT-edk101
0014 */
0015
0016 /dts-v1/;
0017 / {
0018 #address-cells = <1>;
0019 #size-cells = <1>;
0020 compatible = "xlnx,microblaze";
0021 model = "testing";
0022 DDR2_SDRAM: memory@90000000 {
0023 device_type = "memory";
0024 reg = < 0x90000000 0x10000000 >;
0025 } ;
0026 aliases {
0027 ethernet0 = &Hard_Ethernet_MAC;
0028 serial0 = &RS232_Uart_1;
0029 } ;
0030 chosen {
0031 bootargs = "console=ttyUL0,115200 highres=on";
0032 stdout-path = "/plb@0/serial@84000000";
0033 } ;
0034 cpus {
0035 #address-cells = <1>;
0036 #cpus = <0x1>;
0037 #size-cells = <0>;
0038 microblaze_0: cpu@0 {
0039 clock-frequency = <125000000>;
0040 compatible = "xlnx,microblaze-7.10.d";
0041 d-cache-baseaddr = <0x90000000>;
0042 d-cache-highaddr = <0x9fffffff>;
0043 d-cache-line-size = <0x10>;
0044 d-cache-size = <0x2000>;
0045 device_type = "cpu";
0046 i-cache-baseaddr = <0x90000000>;
0047 i-cache-highaddr = <0x9fffffff>;
0048 i-cache-line-size = <0x10>;
0049 i-cache-size = <0x2000>;
0050 model = "microblaze,7.10.d";
0051 reg = <0>;
0052 timebase-frequency = <125000000>;
0053 xlnx,addr-tag-bits = <0xf>;
0054 xlnx,allow-dcache-wr = <0x1>;
0055 xlnx,allow-icache-wr = <0x1>;
0056 xlnx,area-optimized = <0x0>;
0057 xlnx,cache-byte-size = <0x2000>;
0058 xlnx,d-lmb = <0x1>;
0059 xlnx,d-opb = <0x0>;
0060 xlnx,d-plb = <0x1>;
0061 xlnx,data-size = <0x20>;
0062 xlnx,dcache-addr-tag = <0xf>;
0063 xlnx,dcache-always-used = <0x1>;
0064 xlnx,dcache-byte-size = <0x2000>;
0065 xlnx,dcache-line-len = <0x4>;
0066 xlnx,dcache-use-fsl = <0x1>;
0067 xlnx,debug-enabled = <0x1>;
0068 xlnx,div-zero-exception = <0x1>;
0069 xlnx,dopb-bus-exception = <0x0>;
0070 xlnx,dynamic-bus-sizing = <0x1>;
0071 xlnx,edge-is-positive = <0x1>;
0072 xlnx,family = "virtex5";
0073 xlnx,endianness = <0x1>;
0074 xlnx,fpu-exception = <0x1>;
0075 xlnx,fsl-data-size = <0x20>;
0076 xlnx,fsl-exception = <0x0>;
0077 xlnx,fsl-links = <0x0>;
0078 xlnx,i-lmb = <0x1>;
0079 xlnx,i-opb = <0x0>;
0080 xlnx,i-plb = <0x1>;
0081 xlnx,icache-always-used = <0x1>;
0082 xlnx,icache-line-len = <0x4>;
0083 xlnx,icache-use-fsl = <0x1>;
0084 xlnx,ill-opcode-exception = <0x1>;
0085 xlnx,instance = "microblaze_0";
0086 xlnx,interconnect = <0x1>;
0087 xlnx,interrupt-is-edge = <0x0>;
0088 xlnx,iopb-bus-exception = <0x0>;
0089 xlnx,mmu-dtlb-size = <0x4>;
0090 xlnx,mmu-itlb-size = <0x2>;
0091 xlnx,mmu-tlb-access = <0x3>;
0092 xlnx,mmu-zones = <0x10>;
0093 xlnx,number-of-pc-brk = <0x1>;
0094 xlnx,number-of-rd-addr-brk = <0x0>;
0095 xlnx,number-of-wr-addr-brk = <0x0>;
0096 xlnx,opcode-0x0-illegal = <0x1>;
0097 xlnx,pvr = <0x2>;
0098 xlnx,pvr-user1 = <0x0>;
0099 xlnx,pvr-user2 = <0x0>;
0100 xlnx,reset-msr = <0x0>;
0101 xlnx,sco = <0x0>;
0102 xlnx,unaligned-exceptions = <0x1>;
0103 xlnx,use-barrel = <0x1>;
0104 xlnx,use-dcache = <0x1>;
0105 xlnx,use-div = <0x1>;
0106 xlnx,use-ext-brk = <0x1>;
0107 xlnx,use-ext-nm-brk = <0x1>;
0108 xlnx,use-extended-fsl-instr = <0x0>;
0109 xlnx,use-fpu = <0x2>;
0110 xlnx,use-hw-mul = <0x2>;
0111 xlnx,use-icache = <0x1>;
0112 xlnx,use-interrupt = <0x1>;
0113 xlnx,use-mmu = <0x3>;
0114 xlnx,use-msr-instr = <0x1>;
0115 xlnx,use-pcmp-instr = <0x1>;
0116 } ;
0117 } ;
0118 mb_plb: plb@0 {
0119 #address-cells = <1>;
0120 #size-cells = <1>;
0121 compatible = "xlnx,plb-v46-1.03.a", "xlnx,plb-v46-1.00.a", "simple-bus";
0122 ranges ;
0123 FLASH: flash@a0000000 {
0124 bank-width = <2>;
0125 compatible = "xlnx,xps-mch-emc-2.00.a", "cfi-flash";
0126 reg = < 0xa0000000 0x2000000 >;
0127 xlnx,family = "virtex5";
0128 xlnx,include-datawidth-matching-0 = <0x1>;
0129 xlnx,include-datawidth-matching-1 = <0x0>;
0130 xlnx,include-datawidth-matching-2 = <0x0>;
0131 xlnx,include-datawidth-matching-3 = <0x0>;
0132 xlnx,include-negedge-ioregs = <0x0>;
0133 xlnx,include-plb-ipif = <0x1>;
0134 xlnx,include-wrbuf = <0x1>;
0135 xlnx,max-mem-width = <0x10>;
0136 xlnx,mch-native-dwidth = <0x20>;
0137 xlnx,mch-plb-clk-period-ps = <0x1f40>;
0138 xlnx,mch-splb-awidth = <0x20>;
0139 xlnx,mch0-accessbuf-depth = <0x10>;
0140 xlnx,mch0-protocol = <0x0>;
0141 xlnx,mch0-rddatabuf-depth = <0x10>;
0142 xlnx,mch1-accessbuf-depth = <0x10>;
0143 xlnx,mch1-protocol = <0x0>;
0144 xlnx,mch1-rddatabuf-depth = <0x10>;
0145 xlnx,mch2-accessbuf-depth = <0x10>;
0146 xlnx,mch2-protocol = <0x0>;
0147 xlnx,mch2-rddatabuf-depth = <0x10>;
0148 xlnx,mch3-accessbuf-depth = <0x10>;
0149 xlnx,mch3-protocol = <0x0>;
0150 xlnx,mch3-rddatabuf-depth = <0x10>;
0151 xlnx,mem0-width = <0x10>;
0152 xlnx,mem1-width = <0x20>;
0153 xlnx,mem2-width = <0x20>;
0154 xlnx,mem3-width = <0x20>;
0155 xlnx,num-banks-mem = <0x1>;
0156 xlnx,num-channels = <0x0>;
0157 xlnx,priority-mode = <0x0>;
0158 xlnx,synch-mem-0 = <0x0>;
0159 xlnx,synch-mem-1 = <0x0>;
0160 xlnx,synch-mem-2 = <0x0>;
0161 xlnx,synch-mem-3 = <0x0>;
0162 xlnx,synch-pipedelay-0 = <0x2>;
0163 xlnx,synch-pipedelay-1 = <0x2>;
0164 xlnx,synch-pipedelay-2 = <0x2>;
0165 xlnx,synch-pipedelay-3 = <0x2>;
0166 xlnx,tavdv-ps-mem-0 = <0x1adb0>;
0167 xlnx,tavdv-ps-mem-1 = <0x3a98>;
0168 xlnx,tavdv-ps-mem-2 = <0x3a98>;
0169 xlnx,tavdv-ps-mem-3 = <0x3a98>;
0170 xlnx,tcedv-ps-mem-0 = <0x1adb0>;
0171 xlnx,tcedv-ps-mem-1 = <0x3a98>;
0172 xlnx,tcedv-ps-mem-2 = <0x3a98>;
0173 xlnx,tcedv-ps-mem-3 = <0x3a98>;
0174 xlnx,thzce-ps-mem-0 = <0x88b8>;
0175 xlnx,thzce-ps-mem-1 = <0x1b58>;
0176 xlnx,thzce-ps-mem-2 = <0x1b58>;
0177 xlnx,thzce-ps-mem-3 = <0x1b58>;
0178 xlnx,thzoe-ps-mem-0 = <0x1b58>;
0179 xlnx,thzoe-ps-mem-1 = <0x1b58>;
0180 xlnx,thzoe-ps-mem-2 = <0x1b58>;
0181 xlnx,thzoe-ps-mem-3 = <0x1b58>;
0182 xlnx,tlzwe-ps-mem-0 = <0x88b8>;
0183 xlnx,tlzwe-ps-mem-1 = <0x0>;
0184 xlnx,tlzwe-ps-mem-2 = <0x0>;
0185 xlnx,tlzwe-ps-mem-3 = <0x0>;
0186 xlnx,twc-ps-mem-0 = <0x2af8>;
0187 xlnx,twc-ps-mem-1 = <0x3a98>;
0188 xlnx,twc-ps-mem-2 = <0x3a98>;
0189 xlnx,twc-ps-mem-3 = <0x3a98>;
0190 xlnx,twp-ps-mem-0 = <0x11170>;
0191 xlnx,twp-ps-mem-1 = <0x2ee0>;
0192 xlnx,twp-ps-mem-2 = <0x2ee0>;
0193 xlnx,twp-ps-mem-3 = <0x2ee0>;
0194 xlnx,xcl0-linesize = <0x4>;
0195 xlnx,xcl0-writexfer = <0x1>;
0196 xlnx,xcl1-linesize = <0x4>;
0197 xlnx,xcl1-writexfer = <0x1>;
0198 xlnx,xcl2-linesize = <0x4>;
0199 xlnx,xcl2-writexfer = <0x1>;
0200 xlnx,xcl3-linesize = <0x4>;
0201 xlnx,xcl3-writexfer = <0x1>;
0202 } ;
0203 Hard_Ethernet_MAC: xps-ll-temac@81c00000 {
0204 #address-cells = <1>;
0205 #size-cells = <1>;
0206 compatible = "xlnx,compound";
0207 ranges ;
0208 ethernet@81c00000 {
0209 compatible = "xlnx,xps-ll-temac-1.01.b", "xlnx,xps-ll-temac-1.00.a";
0210 interrupt-parent = <&xps_intc_0>;
0211 interrupts = < 5 2 >;
0212 llink-connected = <&PIM3>;
0213 local-mac-address = [ 00 0a 35 00 00 00 ];
0214 reg = < 0x81c00000 0x40 >;
0215 xlnx,bus2core-clk-ratio = <0x1>;
0216 xlnx,phy-type = <0x1>;
0217 xlnx,phyaddr = <0x1>;
0218 xlnx,rxcsum = <0x0>;
0219 xlnx,rxfifo = <0x1000>;
0220 xlnx,temac-type = <0x0>;
0221 xlnx,txcsum = <0x0>;
0222 xlnx,txfifo = <0x1000>;
0223 } ;
0224 } ;
0225 IIC_EEPROM: i2c@81600000 {
0226 compatible = "xlnx,xps-iic-2.00.a";
0227 interrupt-parent = <&xps_intc_0>;
0228 interrupts = < 6 2 >;
0229 reg = < 0x81600000 0x10000 >;
0230 xlnx,clk-freq = <0x7735940>;
0231 xlnx,family = "virtex5";
0232 xlnx,gpo-width = <0x1>;
0233 xlnx,iic-freq = <0x186a0>;
0234 xlnx,scl-inertial-delay = <0x0>;
0235 xlnx,sda-inertial-delay = <0x0>;
0236 xlnx,ten-bit-adr = <0x0>;
0237 } ;
0238 LEDs_8Bit: gpio@81400000 {
0239 compatible = "xlnx,xps-gpio-1.00.a";
0240 interrupt-parent = <&xps_intc_0>;
0241 interrupts = < 7 2 >;
0242 reg = < 0x81400000 0x10000 >;
0243 xlnx,all-inputs = <0x0>;
0244 xlnx,all-inputs-2 = <0x0>;
0245 xlnx,dout-default = <0x0>;
0246 xlnx,dout-default-2 = <0x0>;
0247 xlnx,family = "virtex5";
0248 xlnx,gpio-width = <0x8>;
0249 xlnx,interrupt-present = <0x1>;
0250 xlnx,is-bidir = <0x1>;
0251 xlnx,is-bidir-2 = <0x1>;
0252 xlnx,is-dual = <0x0>;
0253 xlnx,tri-default = <0xffffffff>;
0254 xlnx,tri-default-2 = <0xffffffff>;
0255 #gpio-cells = <2>;
0256 gpio-controller;
0257 } ;
0258
0259 gpio-leds {
0260 compatible = "gpio-leds";
0261
0262 heartbeat {
0263 label = "Heartbeat";
0264 gpios = <&LEDs_8Bit 4 1>;
0265 linux,default-trigger = "heartbeat";
0266 };
0267
0268 yellow {
0269 label = "Yellow";
0270 gpios = <&LEDs_8Bit 5 1>;
0271 };
0272
0273 red {
0274 label = "Red";
0275 gpios = <&LEDs_8Bit 6 1>;
0276 };
0277
0278 green {
0279 label = "Green";
0280 gpios = <&LEDs_8Bit 7 1>;
0281 };
0282 } ;
0283
0284 gpio-restart {
0285 compatible = "gpio-restart";
0286 /*
0287 * FIXME: is this active low or active high?
0288 * the current flag (1) indicates active low.
0289 * delay measures are templates, should be adjusted
0290 * to datasheet or trial-and-error with real hardware.
0291 */
0292 gpios = <&LEDs_8Bit 2 1>;
0293 active-delay = <100>;
0294 inactive-delay = <10>;
0295 wait-delay = <100>;
0296 };
0297
0298 RS232_Uart_1: serial@84000000 {
0299 clock-frequency = <125000000>;
0300 compatible = "xlnx,xps-uartlite-1.00.a";
0301 current-speed = <115200>;
0302 device_type = "serial";
0303 interrupt-parent = <&xps_intc_0>;
0304 interrupts = < 8 0 >;
0305 port-number = <0>;
0306 reg = < 0x84000000 0x10000 >;
0307 xlnx,baudrate = <0x1c200>;
0308 xlnx,data-bits = <0x8>;
0309 xlnx,family = "virtex5";
0310 xlnx,odd-parity = <0x0>;
0311 xlnx,use-parity = <0x0>;
0312 } ;
0313 debug_module: debug@84400000 {
0314 compatible = "xlnx,mdm-1.00.d";
0315 reg = < 0x84400000 0x10000 >;
0316 xlnx,family = "virtex5";
0317 xlnx,interconnect = <0x1>;
0318 xlnx,jtag-chain = <0x2>;
0319 xlnx,mb-dbg-ports = <0x1>;
0320 xlnx,uart-width = <0x8>;
0321 xlnx,use-uart = <0x1>;
0322 xlnx,write-fsl-ports = <0x0>;
0323 } ;
0324 mpmc@90000000 {
0325 #address-cells = <1>;
0326 #size-cells = <1>;
0327 compatible = "xlnx,mpmc-4.02.a";
0328 ranges ;
0329 PIM3: sdma@84600180 {
0330 compatible = "xlnx,ll-dma-1.00.a";
0331 interrupt-parent = <&xps_intc_0>;
0332 interrupts = < 2 2 1 2 >;
0333 reg = < 0x84600180 0x80 >;
0334 } ;
0335 } ;
0336 xps_intc_0: interrupt-controller@81800000 {
0337 #interrupt-cells = <0x2>;
0338 compatible = "xlnx,xps-intc-1.00.a";
0339 interrupt-controller ;
0340 reg = < 0x81800000 0x10000 >;
0341 xlnx,kind-of-intr = <0x100>;
0342 xlnx,num-intr-inputs = <0x9>;
0343 } ;
0344 xps_timer_1: timer@83c00000 {
0345 compatible = "xlnx,xps-timer-1.00.a";
0346 interrupt-parent = <&xps_intc_0>;
0347 interrupts = < 3 2 >;
0348 reg = < 0x83c00000 0x10000 >;
0349 xlnx,count-width = <0x20>;
0350 xlnx,one-timer-only = <0x0>;
0351 } ;
0352 } ;
0353 } ;
