dt-bindings/reset/xlnx-versal-resets.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  *  Copyright (C) 2020 Xilinx, Inc.
0004  */
0005
0006 #ifndef _DT_BINDINGS_VERSAL_RESETS_H
0007 #define _DT_BINDINGS_VERSAL_RESETS_H
0008
0009 #define VERSAL_RST_PMC_POR          (0xc30c001U)
0010 #define VERSAL_RST_PMC              (0xc410002U)
0011 #define VERSAL_RST_PS_POR           (0xc30c003U)
0012 #define VERSAL_RST_PL_POR           (0xc30c004U)
0013 #define VERSAL_RST_NOC_POR          (0xc30c005U)
0014 #define VERSAL_RST_FPD_POR          (0xc30c006U)
0015 #define VERSAL_RST_ACPU_0_POR           (0xc30c007U)
0016 #define VERSAL_RST_ACPU_1_POR           (0xc30c008U)
0017 #define VERSAL_RST_OCM2_POR         (0xc30c009U)
0018 #define VERSAL_RST_PS_SRST          (0xc41000aU)
0019 #define VERSAL_RST_PL_SRST          (0xc41000bU)
0020 #define VERSAL_RST_NOC              (0xc41000cU)
0021 #define VERSAL_RST_NPI              (0xc41000dU)
0022 #define VERSAL_RST_SYS_RST_1            (0xc41000eU)
0023 #define VERSAL_RST_SYS_RST_2            (0xc41000fU)
0024 #define VERSAL_RST_SYS_RST_3            (0xc410010U)
0025 #define VERSAL_RST_FPD              (0xc410011U)
0026 #define VERSAL_RST_PL0              (0xc410012U)
0027 #define VERSAL_RST_PL1              (0xc410013U)
0028 #define VERSAL_RST_PL2              (0xc410014U)
0029 #define VERSAL_RST_PL3              (0xc410015U)
0030 #define VERSAL_RST_APU              (0xc410016U)
0031 #define VERSAL_RST_ACPU_0           (0xc410017U)
0032 #define VERSAL_RST_ACPU_1           (0xc410018U)
0033 #define VERSAL_RST_ACPU_L2          (0xc410019U)
0034 #define VERSAL_RST_ACPU_GIC         (0xc41001aU)
0035 #define VERSAL_RST_RPU_ISLAND           (0xc41001bU)
0036 #define VERSAL_RST_RPU_AMBA         (0xc41001cU)
0037 #define VERSAL_RST_R5_0             (0xc41001dU)
0038 #define VERSAL_RST_R5_1             (0xc41001eU)
0039 #define VERSAL_RST_SYSMON_PMC_SEQ_RST       (0xc41001fU)
0040 #define VERSAL_RST_SYSMON_PMC_CFG_RST       (0xc410020U)
0041 #define VERSAL_RST_SYSMON_FPD_CFG_RST       (0xc410021U)
0042 #define VERSAL_RST_SYSMON_FPD_SEQ_RST       (0xc410022U)
0043 #define VERSAL_RST_SYSMON_LPD           (0xc410023U)
0044 #define VERSAL_RST_PDMA_RST1            (0xc410024U)
0045 #define VERSAL_RST_PDMA_RST0            (0xc410025U)
0046 #define VERSAL_RST_ADMA             (0xc410026U)
0047 #define VERSAL_RST_TIMESTAMP            (0xc410027U)
0048 #define VERSAL_RST_OCM              (0xc410028U)
0049 #define VERSAL_RST_OCM2_RST         (0xc410029U)
0050 #define VERSAL_RST_IPI              (0xc41002aU)
0051 #define VERSAL_RST_SBI              (0xc41002bU)
0052 #define VERSAL_RST_LPD              (0xc41002cU)
0053 #define VERSAL_RST_QSPI             (0xc10402dU)
0054 #define VERSAL_RST_OSPI             (0xc10402eU)
0055 #define VERSAL_RST_SDIO_0           (0xc10402fU)
0056 #define VERSAL_RST_SDIO_1           (0xc104030U)
0057 #define VERSAL_RST_I2C_PMC          (0xc104031U)
0058 #define VERSAL_RST_GPIO_PMC         (0xc104032U)
0059 #define VERSAL_RST_GEM_0            (0xc104033U)
0060 #define VERSAL_RST_GEM_1            (0xc104034U)
0061 #define VERSAL_RST_SPARE            (0xc104035U)
0062 #define VERSAL_RST_USB_0            (0xc104036U)
0063 #define VERSAL_RST_UART_0           (0xc104037U)
0064 #define VERSAL_RST_UART_1           (0xc104038U)
0065 #define VERSAL_RST_SPI_0            (0xc104039U)
0066 #define VERSAL_RST_SPI_1            (0xc10403aU)
0067 #define VERSAL_RST_CAN_FD_0         (0xc10403bU)
0068 #define VERSAL_RST_CAN_FD_1         (0xc10403cU)
0069 #define VERSAL_RST_I2C_0            (0xc10403dU)
0070 #define VERSAL_RST_I2C_1            (0xc10403eU)
0071 #define VERSAL_RST_GPIO_LPD         (0xc10403fU)
0072 #define VERSAL_RST_TTC_0            (0xc104040U)
0073 #define VERSAL_RST_TTC_1            (0xc104041U)
0074 #define VERSAL_RST_TTC_2            (0xc104042U)
0075 #define VERSAL_RST_TTC_3            (0xc104043U)
0076 #define VERSAL_RST_SWDT_FPD         (0xc104044U)
0077 #define VERSAL_RST_SWDT_LPD         (0xc104045U)
0078 #define VERSAL_RST_USB              (0xc104046U)
0079 #define VERSAL_RST_DPC              (0xc208047U)
0080 #define VERSAL_RST_PMCDBG           (0xc208048U)
0081 #define VERSAL_RST_DBG_TRACE            (0xc208049U)
0082 #define VERSAL_RST_DBG_FPD          (0xc20804aU)
0083 #define VERSAL_RST_DBG_TSTMP            (0xc20804bU)
0084 #define VERSAL_RST_RPU0_DBG         (0xc20804cU)
0085 #define VERSAL_RST_RPU1_DBG         (0xc20804dU)
0086 #define VERSAL_RST_HSDP             (0xc20804eU)
0087 #define VERSAL_RST_DBG_LPD          (0xc20804fU)
0088 #define VERSAL_RST_CPM_POR          (0xc30c050U)
0089 #define VERSAL_RST_CPM              (0xc410051U)
0090 #define VERSAL_RST_CPMDBG           (0xc208052U)
0091 #define VERSAL_RST_PCIE_CFG         (0xc410053U)
0092 #define VERSAL_RST_PCIE_CORE0           (0xc410054U)
0093 #define VERSAL_RST_PCIE_CORE1           (0xc410055U)
0094 #define VERSAL_RST_PCIE_DMA         (0xc410056U)
0095 #define VERSAL_RST_CMN              (0xc410057U)
0096 #define VERSAL_RST_L2_0             (0xc410058U)
0097 #define VERSAL_RST_L2_1             (0xc410059U)
0098 #define VERSAL_RST_ADDR_REMAP           (0xc41005aU)
0099 #define VERSAL_RST_CPI0             (0xc41005bU)
0100 #define VERSAL_RST_CPI1             (0xc41005cU)
0101 #define VERSAL_RST_XRAM             (0xc30c05dU)
0102 #define VERSAL_RST_AIE_ARRAY            (0xc10405eU)
0103 #define VERSAL_RST_AIE_SHIM         (0xc10405fU)
0104
0105 #endif