dt-bindings/reset/tegra234-reset.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
0003
0004 #ifndef DT_BINDINGS_RESET_TEGRA234_RESET_H
0005 #define DT_BINDINGS_RESET_TEGRA234_RESET_H
0006
0007 /**
0008  * @file
0009  * @defgroup bpmp_reset_ids Reset ID's
0010  * @brief Identifiers for Resets controllable by firmware
0011  * @{
0012  */
0013 #define TEGRA234_RESET_PEX1_CORE_6      11U
0014 #define TEGRA234_RESET_PEX1_CORE_6_APB      12U
0015 #define TEGRA234_RESET_PEX1_COMMON_APB      13U
0016 #define TEGRA234_RESET_PEX2_CORE_7      14U
0017 #define TEGRA234_RESET_PEX2_CORE_7_APB      15U
0018 #define TEGRA234_RESET_GPCDMA           18U
0019 #define TEGRA234_RESET_HDA          20U
0020 #define TEGRA234_RESET_HDACODEC         21U
0021 #define TEGRA234_RESET_I2C1         24U
0022 #define TEGRA234_RESET_PEX2_CORE_8      25U
0023 #define TEGRA234_RESET_PEX2_CORE_8_APB      26U
0024 #define TEGRA234_RESET_PEX2_CORE_9      27U
0025 #define TEGRA234_RESET_PEX2_CORE_9_APB      28U
0026 #define TEGRA234_RESET_I2C2         29U
0027 #define TEGRA234_RESET_I2C3         30U
0028 #define TEGRA234_RESET_I2C4         31U
0029 #define TEGRA234_RESET_I2C6         32U
0030 #define TEGRA234_RESET_I2C7         33U
0031 #define TEGRA234_RESET_I2C8         34U
0032 #define TEGRA234_RESET_I2C9         35U
0033 #define TEGRA234_RESET_MGBE0_PCS        45U
0034 #define TEGRA234_RESET_MGBE0_MAC        46U
0035 #define TEGRA234_RESET_MGBE1_PCS        49U
0036 #define TEGRA234_RESET_MGBE1_MAC        50U
0037 #define TEGRA234_RESET_MGBE2_PCS        53U
0038 #define TEGRA234_RESET_MGBE2_MAC        54U
0039 #define TEGRA234_RESET_PEX2_CORE_10     56U
0040 #define TEGRA234_RESET_PEX2_CORE_10_APB     57U
0041 #define TEGRA234_RESET_PEX2_COMMON_APB      58U
0042 #define TEGRA234_RESET_PWM1         68U
0043 #define TEGRA234_RESET_PWM2         69U
0044 #define TEGRA234_RESET_PWM3         70U
0045 #define TEGRA234_RESET_PWM4         71U
0046 #define TEGRA234_RESET_PWM5         72U
0047 #define TEGRA234_RESET_PWM6         73U
0048 #define TEGRA234_RESET_PWM7         74U
0049 #define TEGRA234_RESET_PWM8         75U
0050 #define TEGRA234_RESET_QSPI0            76U
0051 #define TEGRA234_RESET_QSPI1            77U
0052 #define TEGRA234_RESET_SDMMC4           85U
0053 #define TEGRA234_RESET_MGBE3_PCS        87U
0054 #define TEGRA234_RESET_MGBE3_MAC        88U
0055 #define TEGRA234_RESET_UARTA            100U
0056 #define TEGRA234_RESET_VIC                      113U
0057 #define TEGRA234_RESET_PEX0_CORE_0      116U
0058 #define TEGRA234_RESET_PEX0_CORE_1      117U
0059 #define TEGRA234_RESET_PEX0_CORE_2      118U
0060 #define TEGRA234_RESET_PEX0_CORE_3      119U
0061 #define TEGRA234_RESET_PEX0_CORE_4      120U
0062 #define TEGRA234_RESET_PEX0_CORE_0_APB      121U
0063 #define TEGRA234_RESET_PEX0_CORE_1_APB      122U
0064 #define TEGRA234_RESET_PEX0_CORE_2_APB      123U
0065 #define TEGRA234_RESET_PEX0_CORE_3_APB      124U
0066 #define TEGRA234_RESET_PEX0_CORE_4_APB      125U
0067 #define TEGRA234_RESET_PEX0_COMMON_APB      126U
0068 #define TEGRA234_RESET_PEX1_CORE_5      129U
0069 #define TEGRA234_RESET_PEX1_CORE_5_APB      130U
0070
0071 /** @} */
0072
0073 #endif