dt-bindings/reset/mt8183-resets.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (c) 2019 MediaTek Inc.
0004  * Author: Yong Liang <yong.liang@mediatek.com>
0005  */
0006
0007 #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8183
0008 #define _DT_BINDINGS_RESET_CONTROLLER_MT8183
0009
0010 /* INFRACFG AO resets */
0011 #define MT8183_INFRACFG_AO_THERM_SW_RST             0
0012 #define MT8183_INFRACFG_AO_USB_TOP_SW_RST           1
0013 #define MT8183_INFRACFG_AO_MM_IOMMU_SW_RST          3
0014 #define MT8183_INFRACFG_AO_MSDC3_SW_RST             4
0015 #define MT8183_INFRACFG_AO_MSDC2_SW_RST             5
0016 #define MT8183_INFRACFG_AO_MSDC1_SW_RST             6
0017 #define MT8183_INFRACFG_AO_MSDC0_SW_RST             7
0018 #define MT8183_INFRACFG_AO_APDMA_SW_RST             9
0019 #define MT8183_INFRACFG_AO_MIMP_D_SW_RST            10
0020 #define MT8183_INFRACFG_AO_BTIF_SW_RST              12
0021 #define MT8183_INFRACFG_AO_DISP_PWM_SW_RST          14
0022 #define MT8183_INFRACFG_AO_AUXADC_SW_RST            15
0023
0024 #define MT8183_INFRACFG_AO_IRTX_SW_RST              32
0025 #define MT8183_INFRACFG_AO_SPI0_SW_RST              33
0026 #define MT8183_INFRACFG_AO_I2C0_SW_RST              34
0027 #define MT8183_INFRACFG_AO_I2C1_SW_RST              35
0028 #define MT8183_INFRACFG_AO_I2C2_SW_RST              36
0029 #define MT8183_INFRACFG_AO_I2C3_SW_RST              37
0030 #define MT8183_INFRACFG_AO_UART0_SW_RST             38
0031 #define MT8183_INFRACFG_AO_UART1_SW_RST             39
0032 #define MT8183_INFRACFG_AO_UART2_SW_RST             40
0033 #define MT8183_INFRACFG_AO_PWM_SW_RST               41
0034 #define MT8183_INFRACFG_AO_SPI1_SW_RST              42
0035 #define MT8183_INFRACFG_AO_I2C4_SW_RST              43
0036 #define MT8183_INFRACFG_AO_DVFSP_SW_RST             44
0037 #define MT8183_INFRACFG_AO_SPI2_SW_RST              45
0038 #define MT8183_INFRACFG_AO_SPI3_SW_RST              46
0039 #define MT8183_INFRACFG_AO_UFSHCI_SW_RST            47
0040
0041 #define MT8183_INFRACFG_AO_PMIC_WRAP_SW_RST         64
0042 #define MT8183_INFRACFG_AO_SPM_SW_RST               65
0043 #define MT8183_INFRACFG_AO_USBSIF_SW_RST            66
0044 #define MT8183_INFRACFG_AO_KP_SW_RST                68
0045 #define MT8183_INFRACFG_AO_APXGPT_SW_RST            69
0046 #define MT8183_INFRACFG_AO_CLDMA_AO_SW_RST          70
0047 #define MT8183_INFRACFG_AO_UNIPRO_UFS_SW_RST            71
0048 #define MT8183_INFRACFG_AO_DX_CC_SW_RST             72
0049 #define MT8183_INFRACFG_AO_UFSPHY_SW_RST            73
0050
0051 #define MT8183_INFRACFG_AO_DX_CC_SEC_SW_RST         96
0052 #define MT8183_INFRACFG_AO_GCE_SW_RST               97
0053 #define MT8183_INFRACFG_AO_CLDMA_SW_RST             98
0054 #define MT8183_INFRACFG_AO_TRNG_SW_RST              99
0055 #define MT8183_INFRACFG_AO_AP_MD_CCIF_1_SW_RST          103
0056 #define MT8183_INFRACFG_AO_AP_MD_CCIF_SW_RST            104
0057 #define MT8183_INFRACFG_AO_I2C1_IMM_SW_RST          105
0058 #define MT8183_INFRACFG_AO_I2C1_ARB_SW_RST          106
0059 #define MT8183_INFRACFG_AO_I2C2_IMM_SW_RST          107
0060 #define MT8183_INFRACFG_AO_I2C2_ARB_SW_RST          108
0061 #define MT8183_INFRACFG_AO_I2C5_SW_RST              109
0062 #define MT8183_INFRACFG_AO_I2C5_IMM_SW_RST          110
0063 #define MT8183_INFRACFG_AO_I2C5_ARB_SW_RST          111
0064 #define MT8183_INFRACFG_AO_SPI4_SW_RST              112
0065 #define MT8183_INFRACFG_AO_SPI5_SW_RST              113
0066 #define MT8183_INFRACFG_AO_INFRA2MFGAXI_CBIP_CLAS_SW_RST    114
0067 #define MT8183_INFRACFG_AO_MFGAXI2INFRA_M0_CBIP_GLAS_OUT_SW_RST 115
0068 #define MT8183_INFRACFG_AO_MFGAXI2INFRA_M1_CBIP_GLAS_OUT_SW_RST 116
0069 #define MT8183_INFRACFG_AO_UFS_AES_SW_RST           117
0070 #define MT8183_INFRACFG_AO_CCU_I2C_IRQ_SW_RST           118
0071 #define MT8183_INFRACFG_AO_CCU_I2C_DMA_SW_RST           119
0072 #define MT8183_INFRACFG_AO_I2C6_SW_RST              120
0073 #define MT8183_INFRACFG_AO_CCU_GALS_SW_RST          121
0074 #define MT8183_INFRACFG_AO_IPU_GALS_SW_RST          122
0075 #define MT8183_INFRACFG_AO_CONN2AP_GALS_SW_RST          123
0076 #define MT8183_INFRACFG_AO_AP_MD_CCIF2_SW_RST           124
0077 #define MT8183_INFRACFG_AO_AP_MD_CCIF3_SW_RST           125
0078 #define MT8183_INFRACFG_AO_I2C7_SW_RST              126
0079 #define MT8183_INFRACFG_AO_I2C8_SW_RST              127
0080
0081 #define MT8183_INFRACFG_SW_RST_NUM              128
0082
0083 /* MMSYS resets */
0084 #define MT8183_MMSYS_SW0_RST_B_DISP_DSI0            25
0085
0086 #define MT8183_TOPRGU_MM_SW_RST                 1
0087 #define MT8183_TOPRGU_MFG_SW_RST                2
0088 #define MT8183_TOPRGU_VENC_SW_RST               3
0089 #define MT8183_TOPRGU_VDEC_SW_RST               4
0090 #define MT8183_TOPRGU_IMG_SW_RST                5
0091 #define MT8183_TOPRGU_MD_SW_RST                 7
0092 #define MT8183_TOPRGU_CONN_SW_RST               9
0093 #define MT8183_TOPRGU_CONN_MCU_SW_RST               12
0094 #define MT8183_TOPRGU_IPU0_SW_RST               14
0095 #define MT8183_TOPRGU_IPU1_SW_RST               15
0096 #define MT8183_TOPRGU_AUDIO_SW_RST              17
0097 #define MT8183_TOPRGU_CAMSYS_SW_RST             18
0098
0099 #define MT8183_TOPRGU_SW_RST_NUM                19
0100
0101 #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8183 */