dt-bindings/reset/mt8135-resets.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (c) 2014 MediaTek Inc.
0004  * Author: Flora Fu, MediaTek
0005  */
0006
0007 #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8135
0008 #define _DT_BINDINGS_RESET_CONTROLLER_MT8135
0009
0010 /* INFRACFG resets */
0011 #define MT8135_INFRA_EMI_REG_RST        0
0012 #define MT8135_INFRA_DRAMC0_A0_RST      1
0013 #define MT8135_INFRA_CCIF0_RST          2
0014 #define MT8135_INFRA_APCIRQ_EINT_RST    3
0015 #define MT8135_INFRA_APXGPT_RST         4
0016 #define MT8135_INFRA_SCPSYS_RST         5
0017 #define MT8135_INFRA_CCIF1_RST          6
0018 #define MT8135_INFRA_PMIC_WRAP_RST      7
0019 #define MT8135_INFRA_KP_RST             8
0020 #define MT8135_INFRA_EMI_RST            32
0021 #define MT8135_INFRA_DRAMC0_RST         34
0022 #define MT8135_INFRA_SMI_RST            35
0023 #define MT8135_INFRA_M4U_RST            36
0024
0025 /*  PERICFG resets */
0026 #define MT8135_PERI_UART0_SW_RST        0
0027 #define MT8135_PERI_UART1_SW_RST        1
0028 #define MT8135_PERI_UART2_SW_RST        2
0029 #define MT8135_PERI_UART3_SW_RST        3
0030 #define MT8135_PERI_IRDA_SW_RST         4
0031 #define MT8135_PERI_PTP_SW_RST          5
0032 #define MT8135_PERI_AP_HIF_SW_RST       6
0033 #define MT8135_PERI_GPCU_SW_RST         7
0034 #define MT8135_PERI_MD_HIF_SW_RST       8
0035 #define MT8135_PERI_NLI_SW_RST          9
0036 #define MT8135_PERI_AUXADC_SW_RST       10
0037 #define MT8135_PERI_DMA_SW_RST          11
0038 #define MT8135_PERI_NFI_SW_RST          14
0039 #define MT8135_PERI_PWM_SW_RST          15
0040 #define MT8135_PERI_THERM_SW_RST        16
0041 #define MT8135_PERI_MSDC0_SW_RST        17
0042 #define MT8135_PERI_MSDC1_SW_RST        18
0043 #define MT8135_PERI_MSDC2_SW_RST        19
0044 #define MT8135_PERI_MSDC3_SW_RST        20
0045 #define MT8135_PERI_I2C0_SW_RST         22
0046 #define MT8135_PERI_I2C1_SW_RST         23
0047 #define MT8135_PERI_I2C2_SW_RST         24
0048 #define MT8135_PERI_I2C3_SW_RST         25
0049 #define MT8135_PERI_I2C4_SW_RST         26
0050 #define MT8135_PERI_I2C5_SW_RST         27
0051 #define MT8135_PERI_I2C6_SW_RST         28
0052 #define MT8135_PERI_USB_SW_RST          29
0053 #define MT8135_PERI_SPI1_SW_RST         33
0054 #define MT8135_PERI_PWRAP_BRIDGE_SW_RST 34
0055
0056 #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8135 */