dt-bindings/reset/hisi%2Chi6220-resets.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /**
0003  * This header provides index for the reset controller
0004  * based on hi6220 SoC.
0005  */
0006 #ifndef _DT_BINDINGS_RESET_CONTROLLER_HI6220
0007 #define _DT_BINDINGS_RESET_CONTROLLER_HI6220
0008
0009 #define PERIPH_RSTDIS0_MMC0             0x000
0010 #define PERIPH_RSTDIS0_MMC1             0x001
0011 #define PERIPH_RSTDIS0_MMC2             0x002
0012 #define PERIPH_RSTDIS0_NANDC            0x003
0013 #define PERIPH_RSTDIS0_USBOTG_BUS       0x004
0014 #define PERIPH_RSTDIS0_POR_PICOPHY      0x005
0015 #define PERIPH_RSTDIS0_USBOTG           0x006
0016 #define PERIPH_RSTDIS0_USBOTG_32K       0x007
0017 #define PERIPH_RSTDIS1_HIFI             0x100
0018 #define PERIPH_RSTDIS1_DIGACODEC        0x105
0019 #define PERIPH_RSTEN2_IPF               0x200
0020 #define PERIPH_RSTEN2_SOCP              0x201
0021 #define PERIPH_RSTEN2_DMAC              0x202
0022 #define PERIPH_RSTEN2_SECENG            0x203
0023 #define PERIPH_RSTEN2_ABB               0x204
0024 #define PERIPH_RSTEN2_HPM0              0x205
0025 #define PERIPH_RSTEN2_HPM1              0x206
0026 #define PERIPH_RSTEN2_HPM2              0x207
0027 #define PERIPH_RSTEN2_HPM3              0x208
0028 #define PERIPH_RSTEN3_CSSYS             0x300
0029 #define PERIPH_RSTEN3_I2C0              0x301
0030 #define PERIPH_RSTEN3_I2C1              0x302
0031 #define PERIPH_RSTEN3_I2C2              0x303
0032 #define PERIPH_RSTEN3_I2C3              0x304
0033 #define PERIPH_RSTEN3_UART1             0x305
0034 #define PERIPH_RSTEN3_UART2             0x306
0035 #define PERIPH_RSTEN3_UART3             0x307
0036 #define PERIPH_RSTEN3_UART4             0x308
0037 #define PERIPH_RSTEN3_SSP               0x309
0038 #define PERIPH_RSTEN3_PWM               0x30a
0039 #define PERIPH_RSTEN3_BLPWM             0x30b
0040 #define PERIPH_RSTEN3_TSENSOR           0x30c
0041 #define PERIPH_RSTEN3_DAPB              0x312
0042 #define PERIPH_RSTEN3_HKADC             0x313
0043 #define PERIPH_RSTEN3_CODEC_SSI         0x314
0044 #define PERIPH_RSTEN3_PMUSSI1           0x316
0045 #define PERIPH_RSTEN8_RS0               0x400
0046 #define PERIPH_RSTEN8_RS2               0x401
0047 #define PERIPH_RSTEN8_RS3               0x402
0048 #define PERIPH_RSTEN8_MS0               0x403
0049 #define PERIPH_RSTEN8_MS2               0x405
0050 #define PERIPH_RSTEN8_XG2RAM0           0x406
0051 #define PERIPH_RSTEN8_X2SRAM_TZMA       0x407
0052 #define PERIPH_RSTEN8_SRAM              0x408
0053 #define PERIPH_RSTEN8_HARQ              0x40a
0054 #define PERIPH_RSTEN8_DDRC              0x40c
0055 #define PERIPH_RSTEN8_DDRC_APB          0x40d
0056 #define PERIPH_RSTEN8_DDRPACK_APB       0x40e
0057 #define PERIPH_RSTEN8_DDRT              0x411
0058 #define PERIPH_RSDIST9_CARM_DAP         0x500
0059 #define PERIPH_RSDIST9_CARM_ATB         0x501
0060 #define PERIPH_RSDIST9_CARM_LBUS        0x502
0061 #define PERIPH_RSDIST9_CARM_POR         0x503
0062 #define PERIPH_RSDIST9_CARM_CORE        0x504
0063 #define PERIPH_RSDIST9_CARM_DBG         0x505
0064 #define PERIPH_RSDIST9_CARM_L2          0x506
0065 #define PERIPH_RSDIST9_CARM_SOCDBG      0x507
0066 #define PERIPH_RSDIST9_CARM_ETM         0x508
0067
0068 #define MEDIA_G3D                       0
0069 #define MEDIA_CODEC_VPU                 2
0070 #define MEDIA_CODEC_JPEG                3
0071 #define MEDIA_ISP                       4
0072 #define MEDIA_ADE                       5
0073 #define MEDIA_MMU                       6
0074 #define MEDIA_XG2RAM1                   7
0075
0076 #define AO_G3D                          1
0077 #define AO_CODECISP                     2
0078 #define AO_MCPU                         4
0079 #define AO_BBPHARQMEM                   5
0080 #define AO_HIFI                         8
0081 #define AO_ACPUSCUL2C                   12
0082
0083 #endif /*_DT_BINDINGS_RESET_CONTROLLER_HI6220*/