dt-bindings/reset/amlogic%2Cmeson-s4-reset.h

0001 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
0002 /*
0003  * Copyright (c) 2021 Amlogic, Inc. All rights reserved.
0004  * Author: Zelong Dong <zelong.dong@amlogic.com>
0005  *
0006  */
0007
0008 #ifndef _DT_BINDINGS_AMLOGIC_MESON_S4_RESET_H
0009 #define _DT_BINDINGS_AMLOGIC_MESON_S4_RESET_H
0010
0011 /*  RESET0                  */
0012 #define RESET_USB_DDR0          0
0013 #define RESET_USB_DDR1          1
0014 #define RESET_USB_DDR2          2
0015 #define RESET_USB_DDR3          3
0016 #define RESET_USBCTRL           4
0017 /*                  5-7 */
0018 #define RESET_USBPHY20          8
0019 #define RESET_USBPHY21          9
0020 /*                  10-15   */
0021 #define RESET_HDMITX_APB        16
0022 #define RESET_BRG_VCBUS_DEC     17
0023 #define RESET_VCBUS         18
0024 #define RESET_VID_PLL_DIV       19
0025 #define RESET_VDI6          20
0026 #define RESET_GE2D          21
0027 #define RESET_HDMITXPHY         22
0028 #define RESET_VID_LOCK          23
0029 #define RESET_VENCL         24
0030 #define RESET_VDAC          25
0031 #define RESET_VENCP         26
0032 #define RESET_VENCI         27
0033 #define RESET_RDMA          28
0034 #define RESET_HDMI_TX           29
0035 #define RESET_VIU           30
0036 #define RESET_VENC          31
0037
0038 /*  RESET1                  */
0039 #define RESET_AUDIO         32
0040 #define RESET_MALI_APB          33
0041 #define RESET_MALI          34
0042 #define RESET_DDR_APB           35
0043 #define RESET_DDR           36
0044 #define RESET_DOS_APB           37
0045 #define RESET_DOS           38
0046 /*                  39-47   */
0047 #define RESET_ETH           48
0048 /*                  49-51   */
0049 #define RESET_DEMOD         52
0050 /*                  53-63   */
0051
0052 /*  RESET2                  */
0053 #define RESET_ABUS_ARB          64
0054 #define RESET_IR_CTRL           65
0055 #define RESET_TEMPSENSOR_DDR        66
0056 #define RESET_TEMPSENSOR_PLL        67
0057 /*                  68-71   */
0058 #define RESET_SMART_CARD        72
0059 #define RESET_SPICC0            73
0060 /*                  74  */
0061 #define RESET_RSA           75
0062 /*                  76-79   */
0063 #define RESET_MSR_CLK           80
0064 #define RESET_SPIFC         81
0065 #define RESET_SARADC            82
0066 /*                  83-87   */
0067 #define RESET_ACODEC            88
0068 #define RESET_CEC           89
0069 #define RESET_AFIFO         90
0070 #define RESET_WATCHDOG          91
0071 /*                  92-95   */
0072
0073 /*  RESET3                  */
0074 /*                  96-127  */
0075
0076 /*  RESET4                  */
0077 /*                  128-131 */
0078 #define RESET_PWM_AB            132
0079 #define RESET_PWM_CD            133
0080 #define RESET_PWM_EF            134
0081 #define RESET_PWM_GH            135
0082 #define RESET_PWM_IJ            136
0083 /*                  137 */
0084 #define RESET_UART_A            138
0085 #define RESET_UART_B            139
0086 #define RESET_UART_C            140
0087 #define RESET_UART_D            141
0088 #define RESET_UART_E            142
0089 /*                  143 */
0090 #define RESET_I2C_S_A           144
0091 #define RESET_I2C_M_A           145
0092 #define RESET_I2C_M_B           146
0093 #define RESET_I2C_M_C           147
0094 #define RESET_I2C_M_D           148
0095 #define RESET_I2C_M_E           149
0096 /*                  150-151 */
0097 #define RESET_SD_EMMC_A         152
0098 #define RESET_SD_EMMC_B         153
0099 #define RESET_NAND_EMMC         154
0100 /*                  155-159 */
0101
0102 /* RESET5 */
0103 #define RESET_BRG_VDEC_PIPL0        160
0104 #define RESET_BRG_HEVCF_PIPL0       161
0105 /*                  162 */
0106 #define RESET_BRG_HCODEC_PIPL0      163
0107 #define RESET_BRG_GE2D_PIPL0        164
0108 #define RESET_BRG_VPU_PIPL0     165
0109 #define RESET_BRG_CPU_PIPL0     166
0110 #define RESET_BRG_MALI_PIPL0        167
0111 /*                  168 */
0112 #define RESET_BRG_MALI_PIPL1        169
0113 /*                  170-171 */
0114 #define RESET_BRG_HEVCF_PIPL1       172
0115 #define RESET_BRG_HEVCB_PIPL1       173
0116 /*                  174-183 */
0117 #define RESET_RAMA          184
0118 /*                  185-186 */
0119 #define RESET_BRG_NIC_VAPB      187
0120 #define RESET_BRG_NIC_DSU       188
0121 #define RESET_BRG_NIC_SYSCLK        189
0122 #define RESET_BRG_NIC_MAIN      190
0123 #define RESET_BRG_NIC_ALL       191
0124
0125 #endif