dt-bindings/reset/altr%2Crst-mgr-a10.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (c) 2014, Steffen Trumtrar <s.trumtrar@pengutronix.de>
0004  */
0005
0006 #ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H
0007 #define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H
0008
0009 /* MPUMODRST */
0010 #define CPU0_RESET      0
0011 #define CPU1_RESET      1
0012 #define WDS_RESET       2
0013 #define SCUPER_RESET        3
0014
0015 /* PER0MODRST */
0016 #define EMAC0_RESET     32
0017 #define EMAC1_RESET     33
0018 #define EMAC2_RESET     34
0019 #define USB0_RESET      35
0020 #define USB1_RESET      36
0021 #define NAND_RESET      37
0022 #define QSPI_RESET      38
0023 #define SDMMC_RESET     39
0024 #define EMAC0_OCP_RESET     40
0025 #define EMAC1_OCP_RESET     41
0026 #define EMAC2_OCP_RESET     42
0027 #define USB0_OCP_RESET      43
0028 #define USB1_OCP_RESET      44
0029 #define NAND_OCP_RESET      45
0030 #define QSPI_OCP_RESET      46
0031 #define SDMMC_OCP_RESET     47
0032 #define DMA_RESET       48
0033 #define SPIM0_RESET     49
0034 #define SPIM1_RESET     50
0035 #define SPIS0_RESET     51
0036 #define SPIS1_RESET     52
0037 #define DMA_OCP_RESET       53
0038 #define EMAC_PTP_RESET      54
0039 /* 55 is empty*/
0040 #define DMAIF0_RESET        56
0041 #define DMAIF1_RESET        57
0042 #define DMAIF2_RESET        58
0043 #define DMAIF3_RESET        59
0044 #define DMAIF4_RESET        60
0045 #define DMAIF5_RESET        61
0046 #define DMAIF6_RESET        62
0047 #define DMAIF7_RESET        63
0048
0049 /* PER1MODRST */
0050 #define L4WD0_RESET     64
0051 #define L4WD1_RESET     65
0052 #define L4SYSTIMER0_RESET   66
0053 #define L4SYSTIMER1_RESET   67
0054 #define SPTIMER0_RESET      68
0055 #define SPTIMER1_RESET      69
0056 /* 70-71 is reserved */
0057 #define I2C0_RESET      72
0058 #define I2C1_RESET      73
0059 #define I2C2_RESET      74
0060 #define I2C3_RESET      75
0061 #define I2C4_RESET      76
0062 /* 77-79 is reserved */
0063 #define UART0_RESET     80
0064 #define UART1_RESET     81
0065 /* 82-87 is reserved */
0066 #define GPIO0_RESET     88
0067 #define GPIO1_RESET     89
0068 #define GPIO2_RESET     90
0069
0070 /* BRGMODRST */
0071 #define HPS2FPGA_RESET      96
0072 #define LWHPS2FPGA_RESET    97
0073 #define FPGA2HPS_RESET      98
0074 #define F2SSDRAM0_RESET     99
0075 #define F2SSDRAM1_RESET     100
0076 #define F2SSDRAM2_RESET     101
0077 #define DDRSCH_RESET        102
0078
0079 /* SYSMODRST*/
0080 #define ROM_RESET       128
0081 #define OCRAM_RESET     129
0082 /* 130 is reserved */
0083 #define FPGAMGR_RESET       131
0084 #define S2F_RESET       132
0085 #define SYSDBG_RESET        133
0086 #define OCRAM_OCP_RESET     134
0087
0088 /* COLDMODRST */
0089 #define CLKMGRCOLD_RESET    160
0090 /* 161-162 is reserved */
0091 #define S2FCOLD_RESET       163
0092 #define TIMESTAMPCOLD_RESET 164
0093 #define TAPCOLD_RESET       165
0094 #define HMCCOLD_RESET       166
0095 #define IOMGRCOLD_RESET     167
0096
0097 /* NRSTMODRST */
0098 #define NRSTPINOE_RESET     192
0099
0100 /* DBGMODRST */
0101 #define DBG_RESET       224
0102 #endif