dt-bindings/power/mt8186-power.h

0001 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
0002 /*
0003  * Copyright (c) 2022 MediaTek Inc.
0004  * Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
0005  */
0006
0007 #ifndef _DT_BINDINGS_POWER_MT8186_POWER_H
0008 #define _DT_BINDINGS_POWER_MT8186_POWER_H
0009
0010 #define MT8186_POWER_DOMAIN_MFG0            0
0011 #define MT8186_POWER_DOMAIN_MFG1            1
0012 #define MT8186_POWER_DOMAIN_MFG2            2
0013 #define MT8186_POWER_DOMAIN_MFG3            3
0014 #define MT8186_POWER_DOMAIN_SSUSB           4
0015 #define MT8186_POWER_DOMAIN_SSUSB_P1            5
0016 #define MT8186_POWER_DOMAIN_DIS             6
0017 #define MT8186_POWER_DOMAIN_IMG             7
0018 #define MT8186_POWER_DOMAIN_IMG2            8
0019 #define MT8186_POWER_DOMAIN_IPE             9
0020 #define MT8186_POWER_DOMAIN_CAM             10
0021 #define MT8186_POWER_DOMAIN_CAM_RAWA            11
0022 #define MT8186_POWER_DOMAIN_CAM_RAWB            12
0023 #define MT8186_POWER_DOMAIN_VENC            13
0024 #define MT8186_POWER_DOMAIN_VDEC            14
0025 #define MT8186_POWER_DOMAIN_WPE             15
0026 #define MT8186_POWER_DOMAIN_CONN_ON         16
0027 #define MT8186_POWER_DOMAIN_CSIRX_TOP           17
0028 #define MT8186_POWER_DOMAIN_ADSP_AO         18
0029 #define MT8186_POWER_DOMAIN_ADSP_INFRA          19
0030 #define MT8186_POWER_DOMAIN_ADSP_TOP            20
0031
0032 #endif /* _DT_BINDINGS_POWER_MT8186_POWER_H */