dt-bindings/pinctrl/samsung.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Samsung's Exynos pinctrl bindings
0004  *
0005  * Copyright (c) 2016 Samsung Electronics Co., Ltd.
0006  *      http://www.samsung.com
0007  * Author: Krzysztof Kozlowski <krzk@kernel.org>
0008  */
0009
0010 #ifndef __DT_BINDINGS_PINCTRL_SAMSUNG_H__
0011 #define __DT_BINDINGS_PINCTRL_SAMSUNG_H__
0012
0013 #define EXYNOS_PIN_PULL_NONE        0
0014 #define EXYNOS_PIN_PULL_DOWN        1
0015 #define EXYNOS_PIN_PULL_UP      3
0016
0017 #define S3C64XX_PIN_PULL_NONE       0
0018 #define S3C64XX_PIN_PULL_DOWN       1
0019 #define S3C64XX_PIN_PULL_UP     2
0020
0021 /* Pin function in power down mode */
0022 #define EXYNOS_PIN_PDN_OUT0     0
0023 #define EXYNOS_PIN_PDN_OUT1     1
0024 #define EXYNOS_PIN_PDN_INPUT        2
0025 #define EXYNOS_PIN_PDN_PREV     3
0026
0027 /* Drive strengths for Exynos3250, Exynos4 (all) and Exynos5250 */
0028 #define EXYNOS4_PIN_DRV_LV1     0
0029 #define EXYNOS4_PIN_DRV_LV2     2
0030 #define EXYNOS4_PIN_DRV_LV3     1
0031 #define EXYNOS4_PIN_DRV_LV4     3
0032
0033 /* Drive strengths for Exynos5260 */
0034 #define EXYNOS5260_PIN_DRV_LV1      0
0035 #define EXYNOS5260_PIN_DRV_LV2      1
0036 #define EXYNOS5260_PIN_DRV_LV4      2
0037 #define EXYNOS5260_PIN_DRV_LV6      3
0038
0039 /*
0040  * Drive strengths for Exynos5410, Exynos542x, Exynos5800 and Exynos850 (except
0041  * GPIO_HSI block)
0042  */
0043 #define EXYNOS5420_PIN_DRV_LV1      0
0044 #define EXYNOS5420_PIN_DRV_LV2      1
0045 #define EXYNOS5420_PIN_DRV_LV3      2
0046 #define EXYNOS5420_PIN_DRV_LV4      3
0047
0048 /* Drive strengths for Exynos5433 */
0049 #define EXYNOS5433_PIN_DRV_FAST_SR1 0
0050 #define EXYNOS5433_PIN_DRV_FAST_SR2 1
0051 #define EXYNOS5433_PIN_DRV_FAST_SR3 2
0052 #define EXYNOS5433_PIN_DRV_FAST_SR4 3
0053 #define EXYNOS5433_PIN_DRV_FAST_SR5 4
0054 #define EXYNOS5433_PIN_DRV_FAST_SR6 5
0055 #define EXYNOS5433_PIN_DRV_SLOW_SR1 8
0056 #define EXYNOS5433_PIN_DRV_SLOW_SR2 9
0057 #define EXYNOS5433_PIN_DRV_SLOW_SR3 0xa
0058 #define EXYNOS5433_PIN_DRV_SLOW_SR4 0xb
0059 #define EXYNOS5433_PIN_DRV_SLOW_SR5 0xc
0060 #define EXYNOS5433_PIN_DRV_SLOW_SR6 0xf
0061
0062 /* Drive strengths for Exynos850 GPIO_HSI block */
0063 #define EXYNOS850_HSI_PIN_DRV_LV1   0   /* 1x   */
0064 #define EXYNOS850_HSI_PIN_DRV_LV1_5 1   /* 1.5x */
0065 #define EXYNOS850_HSI_PIN_DRV_LV2   2   /* 2x   */
0066 #define EXYNOS850_HSI_PIN_DRV_LV2_5 3   /* 2.5x */
0067 #define EXYNOS850_HSI_PIN_DRV_LV3   4   /* 3x   */
0068 #define EXYNOS850_HSI_PIN_DRV_LV4   5   /* 4x   */
0069
0070 #define EXYNOS_PIN_FUNC_INPUT       0
0071 #define EXYNOS_PIN_FUNC_OUTPUT      1
0072 #define EXYNOS_PIN_FUNC_2       2
0073 #define EXYNOS_PIN_FUNC_3       3
0074 #define EXYNOS_PIN_FUNC_4       4
0075 #define EXYNOS_PIN_FUNC_5       5
0076 #define EXYNOS_PIN_FUNC_6       6
0077 #define EXYNOS_PIN_FUNC_EINT        0xf
0078 #define EXYNOS_PIN_FUNC_F       EXYNOS_PIN_FUNC_EINT
0079
0080 /* Drive strengths for Exynos7 FSYS1 block */
0081 #define EXYNOS7_FSYS1_PIN_DRV_LV1   0
0082 #define EXYNOS7_FSYS1_PIN_DRV_LV2   4
0083 #define EXYNOS7_FSYS1_PIN_DRV_LV3   2
0084 #define EXYNOS7_FSYS1_PIN_DRV_LV4   6
0085 #define EXYNOS7_FSYS1_PIN_DRV_LV5   1
0086 #define EXYNOS7_FSYS1_PIN_DRV_LV6   5
0087
0088 #endif /* __DT_BINDINGS_PINCTRL_SAMSUNG_H__ */