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0001 /* SPDX-License-Identifier: GPL-2.0 */ 0002 /* 0003 * MIO pin configuration defines for Xilinx ZynqMP 0004 * 0005 * Copyright (C) 2020 Xilinx, Inc. 0006 */ 0007 0008 #ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H 0009 #define _DT_BINDINGS_PINCTRL_ZYNQMP_H 0010 0011 /* Bit value for different voltage levels */ 0012 #define IO_STANDARD_LVCMOS33 0 0013 #define IO_STANDARD_LVCMOS18 1 0014 0015 /* Bit values for Slew Rates */ 0016 #define SLEW_RATE_FAST 0 0017 #define SLEW_RATE_SLOW 1 0018 0019 #endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */
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