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0001 /* SPDX-License-Identifier: GPL-2.0 */ 0002 /* 0003 * MIO pin configuration defines for Xilinx Zynq 0004 * 0005 * Copyright (C) 2021 Xilinx, Inc. 0006 */ 0007 0008 #ifndef _DT_BINDINGS_PINCTRL_ZYNQ_H 0009 #define _DT_BINDINGS_PINCTRL_ZYNQ_H 0010 0011 /* Configuration options for different power supplies */ 0012 #define IO_STANDARD_LVCMOS18 1 0013 #define IO_STANDARD_LVCMOS25 2 0014 #define IO_STANDARD_LVCMOS33 3 0015 #define IO_STANDARD_HSTL 4 0016 0017 #endif /* _DT_BINDINGS_PINCTRL_ZYNQ_H */
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