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0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * This header provides constants for Tegra pinctrl bindings.
0004  *
0005  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
0006  *
0007  * Author: Laxman Dewangan <ldewangan@nvidia.com>
0008  */
0009 
0010 #ifndef _DT_BINDINGS_PINCTRL_TEGRA_H
0011 #define _DT_BINDINGS_PINCTRL_TEGRA_H
0012 
0013 /*
0014  * Enable/disable for diffeent dt properties. This is applicable for
0015  * properties nvidia,enable-input, nvidia,tristate, nvidia,open-drain,
0016  * nvidia,lock, nvidia,rcv-sel, nvidia,high-speed-mode, nvidia,schmitt.
0017  */
0018 #define TEGRA_PIN_DISABLE               0
0019 #define TEGRA_PIN_ENABLE                1
0020 
0021 #define TEGRA_PIN_PULL_NONE             0
0022 #define TEGRA_PIN_PULL_DOWN             1
0023 #define TEGRA_PIN_PULL_UP               2
0024 
0025 /* Low power mode driver */
0026 #define TEGRA_PIN_LP_DRIVE_DIV_8            0
0027 #define TEGRA_PIN_LP_DRIVE_DIV_4            1
0028 #define TEGRA_PIN_LP_DRIVE_DIV_2            2
0029 #define TEGRA_PIN_LP_DRIVE_DIV_1            3
0030 
0031 /* Rising/Falling slew rate */
0032 #define TEGRA_PIN_SLEW_RATE_FASTEST         0
0033 #define TEGRA_PIN_SLEW_RATE_FAST            1
0034 #define TEGRA_PIN_SLEW_RATE_SLOW            2
0035 #define TEGRA_PIN_SLEW_RATE_SLOWEST         3
0036 
0037 #endif