0001
0002 #ifndef DT_BINDINGS_MEMORY_TEGRA20_MC_H
0003 #define DT_BINDINGS_MEMORY_TEGRA20_MC_H
0004
0005 #define TEGRA20_MC_RESET_AVPC 0
0006 #define TEGRA20_MC_RESET_DC 1
0007 #define TEGRA20_MC_RESET_DCB 2
0008 #define TEGRA20_MC_RESET_EPP 3
0009 #define TEGRA20_MC_RESET_2D 4
0010 #define TEGRA20_MC_RESET_HC 5
0011 #define TEGRA20_MC_RESET_ISP 6
0012 #define TEGRA20_MC_RESET_MPCORE 7
0013 #define TEGRA20_MC_RESET_MPEA 8
0014 #define TEGRA20_MC_RESET_MPEB 9
0015 #define TEGRA20_MC_RESET_MPEC 10
0016 #define TEGRA20_MC_RESET_3D 11
0017 #define TEGRA20_MC_RESET_PPCS 12
0018 #define TEGRA20_MC_RESET_VDE 13
0019 #define TEGRA20_MC_RESET_VI 14
0020
0021 #define TEGRA20_MC_DISPLAY0A 0
0022 #define TEGRA20_MC_DISPLAY0AB 1
0023 #define TEGRA20_MC_DISPLAY0B 2
0024 #define TEGRA20_MC_DISPLAY0BB 3
0025 #define TEGRA20_MC_DISPLAY0C 4
0026 #define TEGRA20_MC_DISPLAY0CB 5
0027 #define TEGRA20_MC_DISPLAY1B 6
0028 #define TEGRA20_MC_DISPLAY1BB 7
0029 #define TEGRA20_MC_EPPUP 8
0030 #define TEGRA20_MC_G2PR 9
0031 #define TEGRA20_MC_G2SR 10
0032 #define TEGRA20_MC_MPEUNIFBR 11
0033 #define TEGRA20_MC_VIRUV 12
0034 #define TEGRA20_MC_AVPCARM7R 13
0035 #define TEGRA20_MC_DISPLAYHC 14
0036 #define TEGRA20_MC_DISPLAYHCB 15
0037 #define TEGRA20_MC_FDCDRD 16
0038 #define TEGRA20_MC_G2DR 17
0039 #define TEGRA20_MC_HOST1XDMAR 18
0040 #define TEGRA20_MC_HOST1XR 19
0041 #define TEGRA20_MC_IDXSRD 20
0042 #define TEGRA20_MC_MPCORER 21
0043 #define TEGRA20_MC_MPE_IPRED 22
0044 #define TEGRA20_MC_MPEAMEMRD 23
0045 #define TEGRA20_MC_MPECSRD 24
0046 #define TEGRA20_MC_PPCSAHBDMAR 25
0047 #define TEGRA20_MC_PPCSAHBSLVR 26
0048 #define TEGRA20_MC_TEXSRD 27
0049 #define TEGRA20_MC_VDEBSEVR 28
0050 #define TEGRA20_MC_VDEMBER 29
0051 #define TEGRA20_MC_VDEMCER 30
0052 #define TEGRA20_MC_VDETPER 31
0053 #define TEGRA20_MC_EPPU 32
0054 #define TEGRA20_MC_EPPV 33
0055 #define TEGRA20_MC_EPPY 34
0056 #define TEGRA20_MC_MPEUNIFBW 35
0057 #define TEGRA20_MC_VIWSB 36
0058 #define TEGRA20_MC_VIWU 37
0059 #define TEGRA20_MC_VIWV 38
0060 #define TEGRA20_MC_VIWY 39
0061 #define TEGRA20_MC_G2DW 40
0062 #define TEGRA20_MC_AVPCARM7W 41
0063 #define TEGRA20_MC_FDCDWR 42
0064 #define TEGRA20_MC_HOST1XW 43
0065 #define TEGRA20_MC_ISPW 44
0066 #define TEGRA20_MC_MPCOREW 45
0067 #define TEGRA20_MC_MPECSWR 46
0068 #define TEGRA20_MC_PPCSAHBDMAW 47
0069 #define TEGRA20_MC_PPCSAHBSLVW 48
0070 #define TEGRA20_MC_VDEBSEVW 49
0071 #define TEGRA20_MC_VDEMBEW 50
0072 #define TEGRA20_MC_VDETPMW 51
0073
0074 #endif
