dt-bindings/memory/mt8195-memory-port.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (c) 2022 MediaTek Inc.
0004  * Author: Yong Wu <yong.wu@mediatek.com>
0005  */
0006 #ifndef _DT_BINDINGS_MEMORY_MT8195_LARB_PORT_H_
0007 #define _DT_BINDINGS_MEMORY_MT8195_LARB_PORT_H_
0008
0009 #include <dt-bindings/memory/mtk-memory-port.h>
0010
0011 /*
0012  * MM IOMMU supports 16GB dma address. We separate it to four ranges:
0013  * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters
0014  * locate in anyone region. BUT:
0015  * a) Make sure all the ports inside a larb are in one range.
0016  * b) The iova of any master can NOT cross the 4G/8G/12G boundary.
0017  *
0018  * This is the suggested mapping in this SoC:
0019  *
0020  * modules    dma-address-region    larbs-ports
0021  * disp         0 ~ 4G                  larb0/1/2/3
0022  * vcodec      4G ~ 8G                  larb19/20/21/22/23/24
0023  * cam/mdp     8G ~ 12G                 the other larbs.
0024  * N/A         12G ~ 16G
0025  * CCU0   0x24000_0000 ~ 0x243ff_ffff   larb18: port 0/1
0026  * CCU1   0x24400_0000 ~ 0x247ff_ffff   larb18: port 2/3
0027  *
0028  * This SoC have two IOMMU HWs, this is the detailed connected information:
0029  * iommu-vdo: larb0/2/5/7/9/10/11/13/17/19/21/24/25/28
0030  * iommu-vpp: larb1/3/4/6/8/12/14/16/18/20/22/23/26/27
0031  */
0032
0033 /* MM IOMMU ports */
0034 /* larb0 */
0035 #define M4U_PORT_L0_DISP_RDMA0          MTK_M4U_ID(0, 0)
0036 #define M4U_PORT_L0_DISP_WDMA0          MTK_M4U_ID(0, 1)
0037 #define M4U_PORT_L0_DISP_OVL0_RDMA0     MTK_M4U_ID(0, 2)
0038 #define M4U_PORT_L0_DISP_OVL0_RDMA1     MTK_M4U_ID(0, 3)
0039 #define M4U_PORT_L0_DISP_OVL0_HDR       MTK_M4U_ID(0, 4)
0040 #define M4U_PORT_L0_DISP_FAKE0          MTK_M4U_ID(0, 5)
0041
0042 /* larb1 */
0043 #define M4U_PORT_L1_DISP_RDMA0          MTK_M4U_ID(1, 0)
0044 #define M4U_PORT_L1_DISP_WDMA0          MTK_M4U_ID(1, 1)
0045 #define M4U_PORT_L1_DISP_OVL0_RDMA0     MTK_M4U_ID(1, 2)
0046 #define M4U_PORT_L1_DISP_OVL0_RDMA1     MTK_M4U_ID(1, 3)
0047 #define M4U_PORT_L1_DISP_OVL0_HDR       MTK_M4U_ID(1, 4)
0048 #define M4U_PORT_L1_DISP_FAKE0          MTK_M4U_ID(1, 5)
0049
0050 /* larb2 */
0051 #define M4U_PORT_L2_MDP_RDMA0           MTK_M4U_ID(2, 0)
0052 #define M4U_PORT_L2_MDP_RDMA2           MTK_M4U_ID(2, 1)
0053 #define M4U_PORT_L2_MDP_RDMA4           MTK_M4U_ID(2, 2)
0054 #define M4U_PORT_L2_MDP_RDMA6           MTK_M4U_ID(2, 3)
0055 #define M4U_PORT_L2_DISP_FAKE1          MTK_M4U_ID(2, 4)
0056
0057 /* larb3 */
0058 #define M4U_PORT_L3_MDP_RDMA1           MTK_M4U_ID(3, 0)
0059 #define M4U_PORT_L3_MDP_RDMA3           MTK_M4U_ID(3, 1)
0060 #define M4U_PORT_L3_MDP_RDMA5           MTK_M4U_ID(3, 2)
0061 #define M4U_PORT_L3_MDP_RDMA7           MTK_M4U_ID(3, 3)
0062 #define M4U_PORT_L3_HDR_DS          MTK_M4U_ID(3, 4)
0063 #define M4U_PORT_L3_HDR_ADL         MTK_M4U_ID(3, 5)
0064 #define M4U_PORT_L3_DISP_FAKE1          MTK_M4U_ID(3, 6)
0065
0066 /* larb4 */
0067 #define M4U_PORT_L4_MDP_RDMA            MTK_M4U_ID(4, 0)
0068 #define M4U_PORT_L4_MDP_FG          MTK_M4U_ID(4, 1)
0069 #define M4U_PORT_L4_MDP_OVL         MTK_M4U_ID(4, 2)
0070 #define M4U_PORT_L4_MDP_WROT            MTK_M4U_ID(4, 3)
0071 #define M4U_PORT_L4_FAKE            MTK_M4U_ID(4, 4)
0072
0073 /* larb5 */
0074 #define M4U_PORT_L5_SVPP1_MDP_RDMA      MTK_M4U_ID(5, 0)
0075 #define M4U_PORT_L5_SVPP1_MDP_FG        MTK_M4U_ID(5, 1)
0076 #define M4U_PORT_L5_SVPP1_MDP_OVL       MTK_M4U_ID(5, 2)
0077 #define M4U_PORT_L5_SVPP1_MDP_WROT      MTK_M4U_ID(5, 3)
0078 #define M4U_PORT_L5_SVPP2_MDP_RDMA      MTK_M4U_ID(5, 4)
0079 #define M4U_PORT_L5_SVPP2_MDP_FG        MTK_M4U_ID(5, 5)
0080 #define M4U_PORT_L5_SVPP2_MDP_WROT      MTK_M4U_ID(5, 6)
0081 #define M4U_PORT_L5_FAKE            MTK_M4U_ID(5, 7)
0082
0083 /* larb6 */
0084 #define M4U_PORT_L6_SVPP3_MDP_RDMA      MTK_M4U_ID(6, 0)
0085 #define M4U_PORT_L6_SVPP3_MDP_FG        MTK_M4U_ID(6, 1)
0086 #define M4U_PORT_L6_SVPP3_MDP_WROT      MTK_M4U_ID(6, 2)
0087 #define M4U_PORT_L6_FAKE            MTK_M4U_ID(6, 3)
0088
0089 /* larb7 */
0090 #define M4U_PORT_L7_IMG_WPE_RDMA0       MTK_M4U_ID(7, 0)
0091 #define M4U_PORT_L7_IMG_WPE_RDMA1       MTK_M4U_ID(7, 1)
0092 #define M4U_PORT_L7_IMG_WPE_WDMA0       MTK_M4U_ID(7, 2)
0093
0094 /* larb8 */
0095 #define M4U_PORT_L8_IMG_WPE_RDMA0       MTK_M4U_ID(8, 0)
0096 #define M4U_PORT_L8_IMG_WPE_RDMA1       MTK_M4U_ID(8, 1)
0097 #define M4U_PORT_L8_IMG_WPE_WDMA0       MTK_M4U_ID(8, 2)
0098
0099 /* larb9 */
0100 #define M4U_PORT_L9_IMG_IMGI_T1_A       MTK_M4U_ID(9, 0)
0101 #define M4U_PORT_L9_IMG_IMGBI_T1_A      MTK_M4U_ID(9, 1)
0102 #define M4U_PORT_L9_IMG_IMGCI_T1_A      MTK_M4U_ID(9, 2)
0103 #define M4U_PORT_L9_IMG_SMTI_T1_A       MTK_M4U_ID(9, 3)
0104 #define M4U_PORT_L9_IMG_TNCSTI_T1_A     MTK_M4U_ID(9, 4)
0105 #define M4U_PORT_L9_IMG_TNCSTI_T4_A     MTK_M4U_ID(9, 5)
0106 #define M4U_PORT_L9_IMG_YUVO_T1_A       MTK_M4U_ID(9, 6)
0107 #define M4U_PORT_L9_IMG_TIMGO_T1_A      MTK_M4U_ID(9, 7)
0108 #define M4U_PORT_L9_IMG_YUVO_T2_A       MTK_M4U_ID(9, 8)
0109 #define M4U_PORT_L9_IMG_IMGI_T1_B       MTK_M4U_ID(9, 9)
0110 #define M4U_PORT_L9_IMG_IMGBI_T1_B      MTK_M4U_ID(9, 10)
0111 #define M4U_PORT_L9_IMG_IMGCI_T1_B      MTK_M4U_ID(9, 11)
0112 #define M4U_PORT_L9_IMG_YUVO_T5_A       MTK_M4U_ID(9, 12)
0113 #define M4U_PORT_L9_IMG_SMTI_T1_B       MTK_M4U_ID(9, 13)
0114 #define M4U_PORT_L9_IMG_TNCSO_T1_A      MTK_M4U_ID(9, 14)
0115 #define M4U_PORT_L9_IMG_SMTO_T1_A       MTK_M4U_ID(9, 15)
0116 #define M4U_PORT_L9_IMG_TNCSTO_T1_A     MTK_M4U_ID(9, 16)
0117 #define M4U_PORT_L9_IMG_YUVO_T2_B       MTK_M4U_ID(9, 17)
0118 #define M4U_PORT_L9_IMG_YUVO_T5_B       MTK_M4U_ID(9, 18)
0119 #define M4U_PORT_L9_IMG_SMTO_T1_B       MTK_M4U_ID(9, 19)
0120
0121 /* larb10 */
0122 #define M4U_PORT_L10_IMG_IMGI_D1_A      MTK_M4U_ID(10, 0)
0123 #define M4U_PORT_L10_IMG_IMGCI_D1_A     MTK_M4U_ID(10, 1)
0124 #define M4U_PORT_L10_IMG_DEPI_D1_A      MTK_M4U_ID(10, 2)
0125 #define M4U_PORT_L10_IMG_DMGI_D1_A      MTK_M4U_ID(10, 3)
0126 #define M4U_PORT_L10_IMG_VIPI_D1_A      MTK_M4U_ID(10, 4)
0127 #define M4U_PORT_L10_IMG_TNRWI_D1_A     MTK_M4U_ID(10, 5)
0128 #define M4U_PORT_L10_IMG_RECI_D1_A      MTK_M4U_ID(10, 6)
0129 #define M4U_PORT_L10_IMG_SMTI_D1_A      MTK_M4U_ID(10, 7)
0130 #define M4U_PORT_L10_IMG_SMTI_D6_A      MTK_M4U_ID(10, 8)
0131 #define M4U_PORT_L10_IMG_PIMGI_P1_A     MTK_M4U_ID(10, 9)
0132 #define M4U_PORT_L10_IMG_PIMGBI_P1_A        MTK_M4U_ID(10, 10)
0133 #define M4U_PORT_L10_IMG_PIMGCI_P1_A        MTK_M4U_ID(10, 11)
0134 #define M4U_PORT_L10_IMG_PIMGI_P1_B     MTK_M4U_ID(10, 12)
0135 #define M4U_PORT_L10_IMG_PIMGBI_P1_B        MTK_M4U_ID(10, 13)
0136 #define M4U_PORT_L10_IMG_PIMGCI_P1_B        MTK_M4U_ID(10, 14)
0137 #define M4U_PORT_L10_IMG_IMG3O_D1_A     MTK_M4U_ID(10, 15)
0138 #define M4U_PORT_L10_IMG_IMG4O_D1_A     MTK_M4U_ID(10, 16)
0139 #define M4U_PORT_L10_IMG_IMG3CO_D1_A        MTK_M4U_ID(10, 17)
0140 #define M4U_PORT_L10_IMG_FEO_D1_A       MTK_M4U_ID(10, 18)
0141 #define M4U_PORT_L10_IMG_IMG2O_D1_A     MTK_M4U_ID(10, 19)
0142 #define M4U_PORT_L10_IMG_TNRWO_D1_A     MTK_M4U_ID(10, 20)
0143 #define M4U_PORT_L10_IMG_SMTO_D1_A      MTK_M4U_ID(10, 21)
0144 #define M4U_PORT_L10_IMG_WROT_P1_A      MTK_M4U_ID(10, 22)
0145 #define M4U_PORT_L10_IMG_WROT_P1_B      MTK_M4U_ID(10, 23)
0146
0147 /* larb11 */
0148 #define M4U_PORT_L11_IMG_WPE_EIS_RDMA0_A    MTK_M4U_ID(11, 0)
0149 #define M4U_PORT_L11_IMG_WPE_EIS_RDMA1_A    MTK_M4U_ID(11, 1)
0150 #define M4U_PORT_L11_IMG_WPE_EIS_WDMA0_A    MTK_M4U_ID(11, 2)
0151 #define M4U_PORT_L11_IMG_WPE_TNR_RDMA0_A    MTK_M4U_ID(11, 3)
0152 #define M4U_PORT_L11_IMG_WPE_TNR_RDMA1_A    MTK_M4U_ID(11, 4)
0153 #define M4U_PORT_L11_IMG_WPE_TNR_WDMA0_A    MTK_M4U_ID(11, 5)
0154 #define M4U_PORT_L11_IMG_WPE_EIS_CQ0_A      MTK_M4U_ID(11, 6)
0155 #define M4U_PORT_L11_IMG_WPE_EIS_CQ1_A      MTK_M4U_ID(11, 7)
0156 #define M4U_PORT_L11_IMG_WPE_TNR_CQ0_A      MTK_M4U_ID(11, 8)
0157 #define M4U_PORT_L11_IMG_WPE_TNR_CQ1_A      MTK_M4U_ID(11, 9)
0158
0159 /* larb12 */
0160 #define M4U_PORT_L12_IMG_FDVT_RDA       MTK_M4U_ID(12, 0)
0161 #define M4U_PORT_L12_IMG_FDVT_RDB       MTK_M4U_ID(12, 1)
0162 #define M4U_PORT_L12_IMG_FDVT_WRA       MTK_M4U_ID(12, 2)
0163 #define M4U_PORT_L12_IMG_FDVT_WRB       MTK_M4U_ID(12, 3)
0164 #define M4U_PORT_L12_IMG_ME_RDMA        MTK_M4U_ID(12, 4)
0165 #define M4U_PORT_L12_IMG_ME_WDMA        MTK_M4U_ID(12, 5)
0166 #define M4U_PORT_L12_IMG_DVS_RDMA       MTK_M4U_ID(12, 6)
0167 #define M4U_PORT_L12_IMG_DVS_WDMA       MTK_M4U_ID(12, 7)
0168 #define M4U_PORT_L12_IMG_DVP_RDMA       MTK_M4U_ID(12, 8)
0169 #define M4U_PORT_L12_IMG_DVP_WDMA       MTK_M4U_ID(12, 9)
0170
0171 /* larb13 */
0172 #define M4U_PORT_L13_CAM_CAMSV_CQI_E1       MTK_M4U_ID(13, 0)
0173 #define M4U_PORT_L13_CAM_CAMSV_CQI_E2       MTK_M4U_ID(13, 1)
0174 #define M4U_PORT_L13_CAM_GCAMSV_A_IMGO_0    MTK_M4U_ID(13, 2)
0175 #define M4U_PORT_L13_CAM_SCAMSV_A_IMGO_0    MTK_M4U_ID(13, 3)
0176 #define M4U_PORT_L13_CAM_GCAMSV_B_IMGO_0    MTK_M4U_ID(13, 4)
0177 #define M4U_PORT_L13_CAM_GCAMSV_B_IMGO_1    MTK_M4U_ID(13, 5)
0178 #define M4U_PORT_L13_CAM_GCAMSV_A_UFEO_0    MTK_M4U_ID(13, 6)
0179 #define M4U_PORT_L13_CAM_GCAMSV_B_UFEO_0    MTK_M4U_ID(13, 7)
0180 #define M4U_PORT_L13_CAM_PDAI_0         MTK_M4U_ID(13, 8)
0181 #define M4U_PORT_L13_CAM_FAKE           MTK_M4U_ID(13, 9)
0182
0183 /* larb14 */
0184 #define M4U_PORT_L14_CAM_GCAMSV_A_IMGO_1    MTK_M4U_ID(14, 0)
0185 #define M4U_PORT_L14_CAM_SCAMSV_A_IMGO_1    MTK_M4U_ID(14, 1)
0186 #define M4U_PORT_L14_CAM_GCAMSV_B_IMGO_0    MTK_M4U_ID(14, 2)
0187 #define M4U_PORT_L14_CAM_GCAMSV_B_IMGO_1    MTK_M4U_ID(14, 3)
0188 #define M4U_PORT_L14_CAM_SCAMSV_B_IMGO_0    MTK_M4U_ID(14, 4)
0189 #define M4U_PORT_L14_CAM_SCAMSV_B_IMGO_1    MTK_M4U_ID(14, 5)
0190 #define M4U_PORT_L14_CAM_IPUI           MTK_M4U_ID(14, 6)
0191 #define M4U_PORT_L14_CAM_IPU2I          MTK_M4U_ID(14, 7)
0192 #define M4U_PORT_L14_CAM_IPUO           MTK_M4U_ID(14, 8)
0193 #define M4U_PORT_L14_CAM_IPU2O          MTK_M4U_ID(14, 9)
0194 #define M4U_PORT_L14_CAM_IPU3O          MTK_M4U_ID(14, 10)
0195 #define M4U_PORT_L14_CAM_GCAMSV_A_UFEO_1    MTK_M4U_ID(14, 11)
0196 #define M4U_PORT_L14_CAM_GCAMSV_B_UFEO_1    MTK_M4U_ID(14, 12)
0197 #define M4U_PORT_L14_CAM_PDAI_1         MTK_M4U_ID(14, 13)
0198 #define M4U_PORT_L14_CAM_PDAO           MTK_M4U_ID(14, 14)
0199
0200 /* larb15: null */
0201
0202 /* larb16 */
0203 #define M4U_PORT_L16_CAM_IMGO_R1        MTK_M4U_ID(16, 0)
0204 #define M4U_PORT_L16_CAM_CQI_R1         MTK_M4U_ID(16, 1)
0205 #define M4U_PORT_L16_CAM_CQI_R2         MTK_M4U_ID(16, 2)
0206 #define M4U_PORT_L16_CAM_BPCI_R1        MTK_M4U_ID(16, 3)
0207 #define M4U_PORT_L16_CAM_LSCI_R1        MTK_M4U_ID(16, 4)
0208 #define M4U_PORT_L16_CAM_RAWI_R2        MTK_M4U_ID(16, 5)
0209 #define M4U_PORT_L16_CAM_RAWI_R3        MTK_M4U_ID(16, 6)
0210 #define M4U_PORT_L16_CAM_UFDI_R2        MTK_M4U_ID(16, 7)
0211 #define M4U_PORT_L16_CAM_UFDI_R3        MTK_M4U_ID(16, 8)
0212 #define M4U_PORT_L16_CAM_RAWI_R4        MTK_M4U_ID(16, 9)
0213 #define M4U_PORT_L16_CAM_RAWI_R5        MTK_M4U_ID(16, 10)
0214 #define M4U_PORT_L16_CAM_AAI_R1         MTK_M4U_ID(16, 11)
0215 #define M4U_PORT_L16_CAM_FHO_R1         MTK_M4U_ID(16, 12)
0216 #define M4U_PORT_L16_CAM_AAO_R1         MTK_M4U_ID(16, 13)
0217 #define M4U_PORT_L16_CAM_TSFSO_R1       MTK_M4U_ID(16, 14)
0218 #define M4U_PORT_L16_CAM_FLKO_R1        MTK_M4U_ID(16, 15)
0219
0220 /* larb17 */
0221 #define M4U_PORT_L17_CAM_YUVO_R1        MTK_M4U_ID(17, 0)
0222 #define M4U_PORT_L17_CAM_YUVO_R3        MTK_M4U_ID(17, 1)
0223 #define M4U_PORT_L17_CAM_YUVCO_R1       MTK_M4U_ID(17, 2)
0224 #define M4U_PORT_L17_CAM_YUVO_R2        MTK_M4U_ID(17, 3)
0225 #define M4U_PORT_L17_CAM_RZH1N2TO_R1        MTK_M4U_ID(17, 4)
0226 #define M4U_PORT_L17_CAM_DRZS4NO_R1     MTK_M4U_ID(17, 5)
0227 #define M4U_PORT_L17_CAM_TNCSO_R1       MTK_M4U_ID(17, 6)
0228
0229 /* larb18 */
0230 #define M4U_PORT_L18_CAM_CCUI           MTK_M4U_ID(18, 0)
0231 #define M4U_PORT_L18_CAM_CCUO           MTK_M4U_ID(18, 1)
0232 #define M4U_PORT_L18_CAM_CCUI2          MTK_M4U_ID(18, 2)
0233 #define M4U_PORT_L18_CAM_CCUO2          MTK_M4U_ID(18, 3)
0234
0235 /* larb19 */
0236 #define M4U_PORT_L19_VENC_RCPU          MTK_M4U_ID(19, 0)
0237 #define M4U_PORT_L19_VENC_REC           MTK_M4U_ID(19, 1)
0238 #define M4U_PORT_L19_VENC_BSDMA         MTK_M4U_ID(19, 2)
0239 #define M4U_PORT_L19_VENC_SV_COMV       MTK_M4U_ID(19, 3)
0240 #define M4U_PORT_L19_VENC_RD_COMV       MTK_M4U_ID(19, 4)
0241 #define M4U_PORT_L19_VENC_NBM_RDMA      MTK_M4U_ID(19, 5)
0242 #define M4U_PORT_L19_VENC_NBM_RDMA_LITE     MTK_M4U_ID(19, 6)
0243 #define M4U_PORT_L19_JPGENC_Y_RDMA      MTK_M4U_ID(19, 7)
0244 #define M4U_PORT_L19_JPGENC_C_RDMA      MTK_M4U_ID(19, 8)
0245 #define M4U_PORT_L19_JPGENC_Q_TABLE     MTK_M4U_ID(19, 9)
0246 #define M4U_PORT_L19_VENC_SUB_W_LUMA        MTK_M4U_ID(19, 10)
0247 #define M4U_PORT_L19_VENC_FCS_NBM_RDMA      MTK_M4U_ID(19, 11)
0248 #define M4U_PORT_L19_JPGENC_BSDMA       MTK_M4U_ID(19, 12)
0249 #define M4U_PORT_L19_JPGDEC_WDMA0       MTK_M4U_ID(19, 13)
0250 #define M4U_PORT_L19_JPGDEC_BSDMA0      MTK_M4U_ID(19, 14)
0251 #define M4U_PORT_L19_VENC_NBM_WDMA      MTK_M4U_ID(19, 15)
0252 #define M4U_PORT_L19_VENC_NBM_WDMA_LITE     MTK_M4U_ID(19, 16)
0253 #define M4U_PORT_L19_VENC_FCS_NBM_WDMA      MTK_M4U_ID(19, 17)
0254 #define M4U_PORT_L19_JPGDEC_WDMA1       MTK_M4U_ID(19, 18)
0255 #define M4U_PORT_L19_JPGDEC_BSDMA1      MTK_M4U_ID(19, 19)
0256 #define M4U_PORT_L19_JPGDEC_BUFF_OFFSET1    MTK_M4U_ID(19, 20)
0257 #define M4U_PORT_L19_JPGDEC_BUFF_OFFSET0    MTK_M4U_ID(19, 21)
0258 #define M4U_PORT_L19_VENC_CUR_LUMA      MTK_M4U_ID(19, 22)
0259 #define M4U_PORT_L19_VENC_CUR_CHROMA        MTK_M4U_ID(19, 23)
0260 #define M4U_PORT_L19_VENC_REF_LUMA      MTK_M4U_ID(19, 24)
0261 #define M4U_PORT_L19_VENC_REF_CHROMA        MTK_M4U_ID(19, 25)
0262 #define M4U_PORT_L19_VENC_SUB_R_CHROMA      MTK_M4U_ID(19, 26)
0263
0264 /* larb20 */
0265 #define M4U_PORT_L20_VENC_RCPU          MTK_M4U_ID(20, 0)
0266 #define M4U_PORT_L20_VENC_REC           MTK_M4U_ID(20, 1)
0267 #define M4U_PORT_L20_VENC_BSDMA         MTK_M4U_ID(20, 2)
0268 #define M4U_PORT_L20_VENC_SV_COMV       MTK_M4U_ID(20, 3)
0269 #define M4U_PORT_L20_VENC_RD_COMV       MTK_M4U_ID(20, 4)
0270 #define M4U_PORT_L20_VENC_NBM_RDMA      MTK_M4U_ID(20, 5)
0271 #define M4U_PORT_L20_VENC_NBM_RDMA_LITE     MTK_M4U_ID(20, 6)
0272 #define M4U_PORT_L20_JPGENC_Y_RDMA      MTK_M4U_ID(20, 7)
0273 #define M4U_PORT_L20_JPGENC_C_RDMA      MTK_M4U_ID(20, 8)
0274 #define M4U_PORT_L20_JPGENC_Q_TABLE     MTK_M4U_ID(20, 9)
0275 #define M4U_PORT_L20_VENC_SUB_W_LUMA        MTK_M4U_ID(20, 10)
0276 #define M4U_PORT_L20_VENC_FCS_NBM_RDMA      MTK_M4U_ID(20, 11)
0277 #define M4U_PORT_L20_JPGENC_BSDMA       MTK_M4U_ID(20, 12)
0278 #define M4U_PORT_L20_JPGDEC_WDMA0       MTK_M4U_ID(20, 13)
0279 #define M4U_PORT_L20_JPGDEC_BSDMA0      MTK_M4U_ID(20, 14)
0280 #define M4U_PORT_L20_VENC_NBM_WDMA      MTK_M4U_ID(20, 15)
0281 #define M4U_PORT_L20_VENC_NBM_WDMA_LITE     MTK_M4U_ID(20, 16)
0282 #define M4U_PORT_L20_VENC_FCS_NBM_WDMA      MTK_M4U_ID(20, 17)
0283 #define M4U_PORT_L20_JPGDEC_WDMA1       MTK_M4U_ID(20, 18)
0284 #define M4U_PORT_L20_JPGDEC_BSDMA1      MTK_M4U_ID(20, 19)
0285 #define M4U_PORT_L20_JPGDEC_BUFF_OFFSET1    MTK_M4U_ID(20, 20)
0286 #define M4U_PORT_L20_JPGDEC_BUFF_OFFSET0    MTK_M4U_ID(20, 21)
0287 #define M4U_PORT_L20_VENC_CUR_LUMA      MTK_M4U_ID(20, 22)
0288 #define M4U_PORT_L20_VENC_CUR_CHROMA        MTK_M4U_ID(20, 23)
0289 #define M4U_PORT_L20_VENC_REF_LUMA      MTK_M4U_ID(20, 24)
0290 #define M4U_PORT_L20_VENC_REF_CHROMA        MTK_M4U_ID(20, 25)
0291 #define M4U_PORT_L20_VENC_SUB_R_CHROMA      MTK_M4U_ID(20, 26)
0292
0293 /* larb21 */
0294 #define M4U_PORT_L21_VDEC_MC_EXT        MTK_M4U_ID(21, 0)
0295 #define M4U_PORT_L21_VDEC_UFO_EXT       MTK_M4U_ID(21, 1)
0296 #define M4U_PORT_L21_VDEC_PP_EXT        MTK_M4U_ID(21, 2)
0297 #define M4U_PORT_L21_VDEC_PRED_RD_EXT       MTK_M4U_ID(21, 3)
0298 #define M4U_PORT_L21_VDEC_PRED_WR_EXT       MTK_M4U_ID(21, 4)
0299 #define M4U_PORT_L21_VDEC_PPWRAP_EXT        MTK_M4U_ID(21, 5)
0300 #define M4U_PORT_L21_VDEC_TILE_EXT      MTK_M4U_ID(21, 6)
0301 #define M4U_PORT_L21_VDEC_VLD_EXT       MTK_M4U_ID(21, 7)
0302 #define M4U_PORT_L21_VDEC_VLD2_EXT      MTK_M4U_ID(21, 8)
0303 #define M4U_PORT_L21_VDEC_AVC_MV_EXT        MTK_M4U_ID(21, 9)
0304
0305 /* larb22 */
0306 #define M4U_PORT_L22_VDEC_MC_EXT        MTK_M4U_ID(22, 0)
0307 #define M4U_PORT_L22_VDEC_UFO_EXT       MTK_M4U_ID(22, 1)
0308 #define M4U_PORT_L22_VDEC_PP_EXT        MTK_M4U_ID(22, 2)
0309 #define M4U_PORT_L22_VDEC_PRED_RD_EXT       MTK_M4U_ID(22, 3)
0310 #define M4U_PORT_L22_VDEC_PRED_WR_EXT       MTK_M4U_ID(22, 4)
0311 #define M4U_PORT_L22_VDEC_PPWRAP_EXT        MTK_M4U_ID(22, 5)
0312 #define M4U_PORT_L22_VDEC_TILE_EXT      MTK_M4U_ID(22, 6)
0313 #define M4U_PORT_L22_VDEC_VLD_EXT       MTK_M4U_ID(22, 7)
0314 #define M4U_PORT_L22_VDEC_VLD2_EXT      MTK_M4U_ID(22, 8)
0315 #define M4U_PORT_L22_VDEC_AVC_MV_EXT        MTK_M4U_ID(22, 9)
0316
0317 /* larb23 */
0318 #define M4U_PORT_L23_VDEC_UFO_ENC_EXT       MTK_M4U_ID(23, 0)
0319 #define M4U_PORT_L23_VDEC_RDMA_EXT      MTK_M4U_ID(23, 1)
0320
0321 /* larb24 */
0322 #define M4U_PORT_L24_VDEC_LAT0_VLD_EXT      MTK_M4U_ID(24, 0)
0323 #define M4U_PORT_L24_VDEC_LAT0_VLD2_EXT     MTK_M4U_ID(24, 1)
0324 #define M4U_PORT_L24_VDEC_LAT0_AVC_MC_EXT   MTK_M4U_ID(24, 2)
0325 #define M4U_PORT_L24_VDEC_LAT0_PRED_RD_EXT  MTK_M4U_ID(24, 3)
0326 #define M4U_PORT_L24_VDEC_LAT0_TILE_EXT     MTK_M4U_ID(24, 4)
0327 #define M4U_PORT_L24_VDEC_LAT0_WDMA_EXT     MTK_M4U_ID(24, 5)
0328 #define M4U_PORT_L24_VDEC_LAT1_VLD_EXT      MTK_M4U_ID(24, 6)
0329 #define M4U_PORT_L24_VDEC_LAT1_VLD2_EXT     MTK_M4U_ID(24, 7)
0330 #define M4U_PORT_L24_VDEC_LAT1_AVC_MC_EXT   MTK_M4U_ID(24, 8)
0331 #define M4U_PORT_L24_VDEC_LAT1_PRED_RD_EXT  MTK_M4U_ID(24, 9)
0332 #define M4U_PORT_L24_VDEC_LAT1_TILE_EXT     MTK_M4U_ID(24, 10)
0333 #define M4U_PORT_L24_VDEC_LAT1_WDMA_EXT     MTK_M4U_ID(24, 11)
0334
0335 /* larb25 */
0336 #define M4U_PORT_L25_CAM_MRAW0_LSCI_M1      MTK_M4U_ID(25, 0)
0337 #define M4U_PORT_L25_CAM_MRAW0_CQI_M1       MTK_M4U_ID(25, 1)
0338 #define M4U_PORT_L25_CAM_MRAW0_CQI_M2       MTK_M4U_ID(25, 2)
0339 #define M4U_PORT_L25_CAM_MRAW0_IMGO_M1      MTK_M4U_ID(25, 3)
0340 #define M4U_PORT_L25_CAM_MRAW0_IMGBO_M1     MTK_M4U_ID(25, 4)
0341 #define M4U_PORT_L25_CAM_MRAW2_LSCI_M1      MTK_M4U_ID(25, 5)
0342 #define M4U_PORT_L25_CAM_MRAW2_CQI_M1       MTK_M4U_ID(25, 6)
0343 #define M4U_PORT_L25_CAM_MRAW2_CQI_M2       MTK_M4U_ID(25, 7)
0344 #define M4U_PORT_L25_CAM_MRAW2_IMGO_M1      MTK_M4U_ID(25, 8)
0345 #define M4U_PORT_L25_CAM_MRAW2_IMGBO_M1     MTK_M4U_ID(25, 9)
0346 #define M4U_PORT_L25_CAM_MRAW0_AFO_M1       MTK_M4U_ID(25, 10)
0347 #define M4U_PORT_L25_CAM_MRAW2_AFO_M1       MTK_M4U_ID(25, 11)
0348
0349 /* larb26 */
0350 #define M4U_PORT_L26_CAM_MRAW1_LSCI_M1      MTK_M4U_ID(26, 0)
0351 #define M4U_PORT_L26_CAM_MRAW1_CQI_M1       MTK_M4U_ID(26, 1)
0352 #define M4U_PORT_L26_CAM_MRAW1_CQI_M2       MTK_M4U_ID(26, 2)
0353 #define M4U_PORT_L26_CAM_MRAW1_IMGO_M1      MTK_M4U_ID(26, 3)
0354 #define M4U_PORT_L26_CAM_MRAW1_IMGBO_M1     MTK_M4U_ID(26, 4)
0355 #define M4U_PORT_L26_CAM_MRAW3_LSCI_M1      MTK_M4U_ID(26, 5)
0356 #define M4U_PORT_L26_CAM_MRAW3_CQI_M1       MTK_M4U_ID(26, 6)
0357 #define M4U_PORT_L26_CAM_MRAW3_CQI_M2       MTK_M4U_ID(26, 7)
0358 #define M4U_PORT_L26_CAM_MRAW3_IMGO_M1      MTK_M4U_ID(26, 8)
0359 #define M4U_PORT_L26_CAM_MRAW3_IMGBO_M1     MTK_M4U_ID(26, 9)
0360 #define M4U_PORT_L26_CAM_MRAW1_AFO_M1       MTK_M4U_ID(26, 10)
0361 #define M4U_PORT_L26_CAM_MRAW3_AFO_M1       MTK_M4U_ID(26, 11)
0362
0363 /* larb27 */
0364 #define M4U_PORT_L27_CAM_IMGO_R1        MTK_M4U_ID(27, 0)
0365 #define M4U_PORT_L27_CAM_CQI_R1         MTK_M4U_ID(27, 1)
0366 #define M4U_PORT_L27_CAM_CQI_R2         MTK_M4U_ID(27, 2)
0367 #define M4U_PORT_L27_CAM_BPCI_R1        MTK_M4U_ID(27, 3)
0368 #define M4U_PORT_L27_CAM_LSCI_R1        MTK_M4U_ID(27, 4)
0369 #define M4U_PORT_L27_CAM_RAWI_R2        MTK_M4U_ID(27, 5)
0370 #define M4U_PORT_L27_CAM_RAWI_R3        MTK_M4U_ID(27, 6)
0371 #define M4U_PORT_L27_CAM_UFDI_R2        MTK_M4U_ID(27, 7)
0372 #define M4U_PORT_L27_CAM_UFDI_R3        MTK_M4U_ID(27, 8)
0373 #define M4U_PORT_L27_CAM_RAWI_R4        MTK_M4U_ID(27, 9)
0374 #define M4U_PORT_L27_CAM_RAWI_R5        MTK_M4U_ID(27, 10)
0375 #define M4U_PORT_L27_CAM_AAI_R1         MTK_M4U_ID(27, 11)
0376 #define M4U_PORT_L27_CAM_FHO_R1         MTK_M4U_ID(27, 12)
0377 #define M4U_PORT_L27_CAM_AAO_R1         MTK_M4U_ID(27, 13)
0378 #define M4U_PORT_L27_CAM_TSFSO_R1       MTK_M4U_ID(27, 14)
0379 #define M4U_PORT_L27_CAM_FLKO_R1        MTK_M4U_ID(27, 15)
0380
0381 /* larb28 */
0382 #define M4U_PORT_L28_CAM_YUVO_R1        MTK_M4U_ID(28, 0)
0383 #define M4U_PORT_L28_CAM_YUVO_R3        MTK_M4U_ID(28, 1)
0384 #define M4U_PORT_L28_CAM_YUVCO_R1       MTK_M4U_ID(28, 2)
0385 #define M4U_PORT_L28_CAM_YUVO_R2        MTK_M4U_ID(28, 3)
0386 #define M4U_PORT_L28_CAM_RZH1N2TO_R1        MTK_M4U_ID(28, 4)
0387 #define M4U_PORT_L28_CAM_DRZS4NO_R1     MTK_M4U_ID(28, 5)
0388 #define M4U_PORT_L28_CAM_TNCSO_R1       MTK_M4U_ID(28, 6)
0389
0390 /* Infra iommu ports */
0391 /* PCIe1: read: BIT16; write BIT17. */
0392 #define IOMMU_PORT_INFRA_PCIE1          MTK_IFAIOMMU_PERI_ID(16)
0393 /* PCIe0: read: BIT18; write BIT19. */
0394 #define IOMMU_PORT_INFRA_PCIE0          MTK_IFAIOMMU_PERI_ID(18)
0395 #define IOMMU_PORT_INFRA_SSUSB_P3_R     MTK_IFAIOMMU_PERI_ID(20)
0396 #define IOMMU_PORT_INFRA_SSUSB_P3_W     MTK_IFAIOMMU_PERI_ID(21)
0397 #define IOMMU_PORT_INFRA_SSUSB_P2_R     MTK_IFAIOMMU_PERI_ID(22)
0398 #define IOMMU_PORT_INFRA_SSUSB_P2_W     MTK_IFAIOMMU_PERI_ID(23)
0399 #define IOMMU_PORT_INFRA_SSUSB_P1_1_R       MTK_IFAIOMMU_PERI_ID(24)
0400 #define IOMMU_PORT_INFRA_SSUSB_P1_1_W       MTK_IFAIOMMU_PERI_ID(25)
0401 #define IOMMU_PORT_INFRA_SSUSB_P1_0_R       MTK_IFAIOMMU_PERI_ID(26)
0402 #define IOMMU_PORT_INFRA_SSUSB_P1_0_W       MTK_IFAIOMMU_PERI_ID(27)
0403 #define IOMMU_PORT_INFRA_SSUSB2_R       MTK_IFAIOMMU_PERI_ID(28)
0404 #define IOMMU_PORT_INFRA_SSUSB2_W       MTK_IFAIOMMU_PERI_ID(29)
0405 #define IOMMU_PORT_INFRA_SSUSB_R        MTK_IFAIOMMU_PERI_ID(30)
0406 #define IOMMU_PORT_INFRA_SSUSB_W        MTK_IFAIOMMU_PERI_ID(31)
0407
0408 #endif