dt-bindings/memory/mt2701-larb-port.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (c) 2015 MediaTek Inc.
0004  * Author: Honghui Zhang <honghui.zhang@mediatek.com>
0005  */
0006
0007 #ifndef _DT_BINDINGS_MEMORY_MT2701_LARB_PORT_H_
0008 #define _DT_BINDINGS_MEMORY_MT2701_LARB_PORT_H_
0009
0010 /*
0011  * Mediatek m4u generation 1 such as mt2701 has flat m4u port numbers,
0012  * the first port's id for larb[N] would be the last port's id of larb[N - 1]
0013  * plus one while larb[0]'s first port number is 0. The definition of
0014  * MT2701_M4U_ID_LARBx is following HW register spec.
0015  * But m4u generation 2 like mt8173 have different port number, it use fixed
0016  * offset for each larb, the first port's id for larb[N] would be (N * 32).
0017  */
0018 #define LARB0_PORT_OFFSET       0
0019 #define LARB1_PORT_OFFSET       11
0020 #define LARB2_PORT_OFFSET       21
0021 #define LARB3_PORT_OFFSET       44
0022
0023 #define MT2701_M4U_ID_LARB0(port)   ((port) + LARB0_PORT_OFFSET)
0024 #define MT2701_M4U_ID_LARB1(port)   ((port) + LARB1_PORT_OFFSET)
0025 #define MT2701_M4U_ID_LARB2(port)   ((port) + LARB2_PORT_OFFSET)
0026
0027 /* Port define for larb0 */
0028 #define MT2701_M4U_PORT_DISP_OVL_0      MT2701_M4U_ID_LARB0(0)
0029 #define MT2701_M4U_PORT_DISP_RDMA1      MT2701_M4U_ID_LARB0(1)
0030 #define MT2701_M4U_PORT_DISP_RDMA       MT2701_M4U_ID_LARB0(2)
0031 #define MT2701_M4U_PORT_DISP_WDMA       MT2701_M4U_ID_LARB0(3)
0032 #define MT2701_M4U_PORT_MM_CMDQ         MT2701_M4U_ID_LARB0(4)
0033 #define MT2701_M4U_PORT_MDP_RDMA        MT2701_M4U_ID_LARB0(5)
0034 #define MT2701_M4U_PORT_MDP_WDMA        MT2701_M4U_ID_LARB0(6)
0035 #define MT2701_M4U_PORT_MDP_ROTO        MT2701_M4U_ID_LARB0(7)
0036 #define MT2701_M4U_PORT_MDP_ROTCO       MT2701_M4U_ID_LARB0(8)
0037 #define MT2701_M4U_PORT_MDP_ROTVO       MT2701_M4U_ID_LARB0(9)
0038 #define MT2701_M4U_PORT_MDP_RDMA1       MT2701_M4U_ID_LARB0(10)
0039
0040 /* Port define for larb1 */
0041 #define MT2701_M4U_PORT_VDEC_MC_EXT     MT2701_M4U_ID_LARB1(0)
0042 #define MT2701_M4U_PORT_VDEC_PP_EXT     MT2701_M4U_ID_LARB1(1)
0043 #define MT2701_M4U_PORT_VDEC_PPWRAP_EXT     MT2701_M4U_ID_LARB1(2)
0044 #define MT2701_M4U_PORT_VDEC_AVC_MV_EXT     MT2701_M4U_ID_LARB1(3)
0045 #define MT2701_M4U_PORT_VDEC_PRED_RD_EXT    MT2701_M4U_ID_LARB1(4)
0046 #define MT2701_M4U_PORT_VDEC_PRED_WR_EXT    MT2701_M4U_ID_LARB1(5)
0047 #define MT2701_M4U_PORT_VDEC_VLD_EXT        MT2701_M4U_ID_LARB1(6)
0048 #define MT2701_M4U_PORT_VDEC_VLD2_EXT       MT2701_M4U_ID_LARB1(7)
0049 #define MT2701_M4U_PORT_VDEC_TILE_EXT       MT2701_M4U_ID_LARB1(8)
0050 #define MT2701_M4U_PORT_VDEC_IMG_RESZ_EXT   MT2701_M4U_ID_LARB1(9)
0051
0052 /* Port define for larb2 */
0053 #define MT2701_M4U_PORT_VENC_RCPU       MT2701_M4U_ID_LARB2(0)
0054 #define MT2701_M4U_PORT_VENC_REC_FRM        MT2701_M4U_ID_LARB2(1)
0055 #define MT2701_M4U_PORT_VENC_BSDMA      MT2701_M4U_ID_LARB2(2)
0056 #define MT2701_M4U_PORT_JPGENC_RDMA     MT2701_M4U_ID_LARB2(3)
0057 #define MT2701_M4U_PORT_VENC_LT_RCPU        MT2701_M4U_ID_LARB2(4)
0058 #define MT2701_M4U_PORT_VENC_LT_REC_FRM     MT2701_M4U_ID_LARB2(5)
0059 #define MT2701_M4U_PORT_VENC_LT_BSDMA       MT2701_M4U_ID_LARB2(6)
0060 #define MT2701_M4U_PORT_JPGDEC_BSDMA        MT2701_M4U_ID_LARB2(7)
0061 #define MT2701_M4U_PORT_VENC_SV_COMV        MT2701_M4U_ID_LARB2(8)
0062 #define MT2701_M4U_PORT_VENC_RD_COMV        MT2701_M4U_ID_LARB2(9)
0063 #define MT2701_M4U_PORT_JPGENC_BSDMA        MT2701_M4U_ID_LARB2(10)
0064 #define MT2701_M4U_PORT_VENC_CUR_LUMA       MT2701_M4U_ID_LARB2(11)
0065 #define MT2701_M4U_PORT_VENC_CUR_CHROMA     MT2701_M4U_ID_LARB2(12)
0066 #define MT2701_M4U_PORT_VENC_REF_LUMA       MT2701_M4U_ID_LARB2(13)
0067 #define MT2701_M4U_PORT_VENC_REF_CHROMA     MT2701_M4U_ID_LARB2(14)
0068 #define MT2701_M4U_PORT_IMG_RESZ        MT2701_M4U_ID_LARB2(15)
0069 #define MT2701_M4U_PORT_VENC_LT_SV_COMV     MT2701_M4U_ID_LARB2(16)
0070 #define MT2701_M4U_PORT_VENC_LT_RD_COMV     MT2701_M4U_ID_LARB2(17)
0071 #define MT2701_M4U_PORT_VENC_LT_CUR_LUMA    MT2701_M4U_ID_LARB2(18)
0072 #define MT2701_M4U_PORT_VENC_LT_CUR_CHROMA  MT2701_M4U_ID_LARB2(19)
0073 #define MT2701_M4U_PORT_VENC_LT_REF_LUMA    MT2701_M4U_ID_LARB2(20)
0074 #define MT2701_M4U_PORT_VENC_LT_REF_CHROMA  MT2701_M4U_ID_LARB2(21)
0075 #define MT2701_M4U_PORT_JPGDEC_WDMA     MT2701_M4U_ID_LARB2(22)
0076
0077 #endif