dt-bindings/clock/stih407-clks.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * This header provides constants clk index STMicroelectronics
0004  * STiH407 SoC.
0005  */
0006 #ifndef _DT_BINDINGS_CLK_STIH407
0007 #define _DT_BINDINGS_CLK_STIH407
0008
0009 /* CLOCKGEN A0 */
0010 #define CLK_IC_LMI0     0
0011 #define CLK_IC_LMI1     1
0012
0013 /* CLOCKGEN C0 */
0014 #define CLK_ICN_GPU     0
0015 #define CLK_FDMA        1
0016 #define CLK_NAND        2
0017 #define CLK_HVA         3
0018 #define CLK_PROC_STFE       4
0019 #define CLK_PROC_TP     5
0020 #define CLK_RX_ICN_DMU      6
0021 #define CLK_RX_ICN_DISP_0   6
0022 #define CLK_RX_ICN_DISP_1   6
0023 #define CLK_RX_ICN_HVA      7
0024 #define CLK_RX_ICN_TS       7
0025 #define CLK_ICN_CPU     8
0026 #define CLK_TX_ICN_DMU      9
0027 #define CLK_TX_ICN_HVA      9
0028 #define CLK_TX_ICN_TS       9
0029 #define CLK_ICN_COMPO       9
0030 #define CLK_MMC_0       10
0031 #define CLK_MMC_1       11
0032 #define CLK_JPEGDEC     12
0033 #define CLK_ICN_REG     13
0034 #define CLK_TRACE_A9        13
0035 #define CLK_PTI_STM     13
0036 #define CLK_EXT2F_A9        13
0037 #define CLK_IC_BDISP_0      14
0038 #define CLK_IC_BDISP_1      15
0039 #define CLK_PP_DMU      16
0040 #define CLK_VID_DMU     17
0041 #define CLK_DSS_LPC     18
0042 #define CLK_ST231_AUD_0     19
0043 #define CLK_ST231_GP_0      19
0044 #define CLK_ST231_GP_1      20
0045 #define CLK_ST231_DMU       21
0046 #define CLK_ICN_LMI     22
0047 #define CLK_TX_ICN_DISP_0   23
0048 #define CLK_TX_ICN_DISP_1   23
0049 #define CLK_ICN_SBC     24
0050 #define CLK_STFE_FRC2       25
0051 #define CLK_ETH_PHY     26
0052 #define CLK_ETH_REF_PHYCLK  27
0053 #define CLK_FLASH_PROMIP    28
0054 #define CLK_MAIN_DISP       29
0055 #define CLK_AUX_DISP        30
0056 #define CLK_COMPO_DVP       31
0057
0058 /* CLOCKGEN D0 */
0059 #define CLK_PCM_0       0
0060 #define CLK_PCM_1       1
0061 #define CLK_PCM_2       2
0062 #define CLK_SPDIFF      3
0063
0064 /* CLOCKGEN D2 */
0065 #define CLK_PIX_MAIN_DISP   0
0066 #define CLK_PIX_PIP     1
0067 #define CLK_PIX_GDP1        2
0068 #define CLK_PIX_GDP2        3
0069 #define CLK_PIX_GDP3        4
0070 #define CLK_PIX_GDP4        5
0071 #define CLK_PIX_AUX_DISP    6
0072 #define CLK_DENC        7
0073 #define CLK_PIX_HDDAC       8
0074 #define CLK_HDDAC       9
0075 #define CLK_SDDAC       10
0076 #define CLK_PIX_DVO     11
0077 #define CLK_DVO         12
0078 #define CLK_PIX_HDMI        13
0079 #define CLK_TMDS_HDMI       14
0080 #define CLK_REF_HDMIPHY     15
0081
0082 /* CLOCKGEN D3 */
0083 #define CLK_STFE_FRC1       0
0084 #define CLK_TSOUT_0     1
0085 #define CLK_TSOUT_1     2
0086 #define CLK_MCHI        3
0087 #define CLK_VSENS_COMPO     4
0088 #define CLK_FRC1_REMOTE     5
0089 #define CLK_LPC_0       6
0090 #define CLK_LPC_1       7
0091 #endif