dt-bindings/clock/sh73a0-clock.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright 2014 Ulrich Hecht
0004  */
0005
0006 #ifndef __DT_BINDINGS_CLOCK_SH73A0_H__
0007 #define __DT_BINDINGS_CLOCK_SH73A0_H__
0008
0009 /* CPG */
0010 #define SH73A0_CLK_MAIN     0
0011 #define SH73A0_CLK_PLL0     1
0012 #define SH73A0_CLK_PLL1     2
0013 #define SH73A0_CLK_PLL2     3
0014 #define SH73A0_CLK_PLL3     4
0015 #define SH73A0_CLK_DSI0PHY  5
0016 #define SH73A0_CLK_DSI1PHY  6
0017 #define SH73A0_CLK_ZG       7
0018 #define SH73A0_CLK_M3       8
0019 #define SH73A0_CLK_B        9
0020 #define SH73A0_CLK_M1       10
0021 #define SH73A0_CLK_M2       11
0022 #define SH73A0_CLK_Z        12
0023 #define SH73A0_CLK_ZX       13
0024 #define SH73A0_CLK_HP       14
0025
0026 /* MSTP0 */
0027 #define SH73A0_CLK_IIC2     1
0028 #define SH73A0_CLK_MSIOF0   0
0029
0030 /* MSTP1 */
0031 #define SH73A0_CLK_CEU1     29
0032 #define SH73A0_CLK_CSI2_RX1 28
0033 #define SH73A0_CLK_CEU0     27
0034 #define SH73A0_CLK_CSI2_RX0 26
0035 #define SH73A0_CLK_TMU0     25
0036 #define SH73A0_CLK_DSITX0   18
0037 #define SH73A0_CLK_IIC0     16
0038 #define SH73A0_CLK_SGX      12
0039 #define SH73A0_CLK_LCDC0    0
0040
0041 /* MSTP2 */
0042 #define SH73A0_CLK_SCIFA7   19
0043 #define SH73A0_CLK_SY_DMAC  18
0044 #define SH73A0_CLK_MP_DMAC  17
0045 #define SH73A0_CLK_MSIOF3   15
0046 #define SH73A0_CLK_MSIOF1   8
0047 #define SH73A0_CLK_SCIFA5   7
0048 #define SH73A0_CLK_SCIFB    6
0049 #define SH73A0_CLK_MSIOF2   5
0050 #define SH73A0_CLK_SCIFA0   4
0051 #define SH73A0_CLK_SCIFA1   3
0052 #define SH73A0_CLK_SCIFA2   2
0053 #define SH73A0_CLK_SCIFA3   1
0054 #define SH73A0_CLK_SCIFA4   0
0055
0056 /* MSTP3 */
0057 #define SH73A0_CLK_SCIFA6   31
0058 #define SH73A0_CLK_CMT1     29
0059 #define SH73A0_CLK_FSI      28
0060 #define SH73A0_CLK_IRDA     25
0061 #define SH73A0_CLK_IIC1     23
0062 #define SH73A0_CLK_USB      22
0063 #define SH73A0_CLK_FLCTL    15
0064 #define SH73A0_CLK_SDHI0    14
0065 #define SH73A0_CLK_SDHI1    13
0066 #define SH73A0_CLK_MMCIF0   12
0067 #define SH73A0_CLK_SDHI2    11
0068 #define SH73A0_CLK_TPU0     4
0069 #define SH73A0_CLK_TPU1     3
0070 #define SH73A0_CLK_TPU2     2
0071 #define SH73A0_CLK_TPU3     1
0072 #define SH73A0_CLK_TPU4     0
0073
0074 /* MSTP4 */
0075 #define SH73A0_CLK_IIC3     11
0076 #define SH73A0_CLK_IIC4     10
0077 #define SH73A0_CLK_KEYSC    3
0078
0079 /* MSTP5 */
0080 #define SH73A0_CLK_INTCA0   8
0081
0082 #endif