dt-bindings/clock/r7s72100-clock.h

0001 /* SPDX-License-Identifier: GPL-2.0
0002  *
0003  * Copyright (C) 2014 Renesas Solutions Corp.
0004  * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
0005  */
0006
0007 #ifndef __DT_BINDINGS_CLOCK_R7S72100_H__
0008 #define __DT_BINDINGS_CLOCK_R7S72100_H__
0009
0010 #define R7S72100_CLK_PLL    0
0011 #define R7S72100_CLK_I      1
0012 #define R7S72100_CLK_G      2
0013
0014 /* MSTP2 */
0015 #define R7S72100_CLK_CORESIGHT  0
0016
0017 /* MSTP3 */
0018 #define R7S72100_CLK_IEBUS  7
0019 #define R7S72100_CLK_IRDA   6
0020 #define R7S72100_CLK_LIN0   5
0021 #define R7S72100_CLK_LIN1   4
0022 #define R7S72100_CLK_MTU2   3
0023 #define R7S72100_CLK_CAN    2
0024 #define R7S72100_CLK_ADCPWR 1
0025 #define R7S72100_CLK_PWM    0
0026
0027 /* MSTP4 */
0028 #define R7S72100_CLK_SCIF0  7
0029 #define R7S72100_CLK_SCIF1  6
0030 #define R7S72100_CLK_SCIF2  5
0031 #define R7S72100_CLK_SCIF3  4
0032 #define R7S72100_CLK_SCIF4  3
0033 #define R7S72100_CLK_SCIF5  2
0034 #define R7S72100_CLK_SCIF6  1
0035 #define R7S72100_CLK_SCIF7  0
0036
0037 /* MSTP5 */
0038 #define R7S72100_CLK_SCI0   7
0039 #define R7S72100_CLK_SCI1   6
0040 #define R7S72100_CLK_SG0    5
0041 #define R7S72100_CLK_SG1    4
0042 #define R7S72100_CLK_SG2    3
0043 #define R7S72100_CLK_SG3    2
0044 #define R7S72100_CLK_OSTM0  1
0045 #define R7S72100_CLK_OSTM1  0
0046
0047 /* MSTP6 */
0048 #define R7S72100_CLK_ADC    7
0049 #define R7S72100_CLK_CEU    6
0050 #define R7S72100_CLK_DOC0   5
0051 #define R7S72100_CLK_DOC1   4
0052 #define R7S72100_CLK_DRC0   3
0053 #define R7S72100_CLK_DRC1   2
0054 #define R7S72100_CLK_JCU    1
0055 #define R7S72100_CLK_RTC    0
0056
0057 /* MSTP7 */
0058 #define R7S72100_CLK_VDEC0  7
0059 #define R7S72100_CLK_VDEC1  6
0060 #define R7S72100_CLK_ETHER  4
0061 #define R7S72100_CLK_NAND   3
0062 #define R7S72100_CLK_USB0   1
0063 #define R7S72100_CLK_USB1   0
0064
0065 /* MSTP8 */
0066 #define R7S72100_CLK_IMR0   7
0067 #define R7S72100_CLK_IMR1   6
0068 #define R7S72100_CLK_IMRDISP    5
0069 #define R7S72100_CLK_MMCIF  4
0070 #define R7S72100_CLK_MLB    3
0071 #define R7S72100_CLK_ETHAVB 2
0072 #define R7S72100_CLK_SCUX   1
0073
0074 /* MSTP9 */
0075 #define R7S72100_CLK_I2C0   7
0076 #define R7S72100_CLK_I2C1   6
0077 #define R7S72100_CLK_I2C2   5
0078 #define R7S72100_CLK_I2C3   4
0079 #define R7S72100_CLK_SPIBSC0    3
0080 #define R7S72100_CLK_SPIBSC1    2
0081 #define R7S72100_CLK_VDC50  1   /* and LVDS */
0082 #define R7S72100_CLK_VDC51  0
0083
0084 /* MSTP10 */
0085 #define R7S72100_CLK_SPI0   7
0086 #define R7S72100_CLK_SPI1   6
0087 #define R7S72100_CLK_SPI2   5
0088 #define R7S72100_CLK_SPI3   4
0089 #define R7S72100_CLK_SPI4   3
0090 #define R7S72100_CLK_CDROM  2
0091 #define R7S72100_CLK_SPDIF  1
0092 #define R7S72100_CLK_RGPVG2 0
0093
0094 /* MSTP11 */
0095 #define R7S72100_CLK_SSI0   5
0096 #define R7S72100_CLK_SSI1   4
0097 #define R7S72100_CLK_SSI2   3
0098 #define R7S72100_CLK_SSI3   2
0099 #define R7S72100_CLK_SSI4   1
0100 #define R7S72100_CLK_SSI5   0
0101
0102 /* MSTP12 */
0103 #define R7S72100_CLK_SDHI00 3
0104 #define R7S72100_CLK_SDHI01 2
0105 #define R7S72100_CLK_SDHI10 1
0106 #define R7S72100_CLK_SDHI11 0
0107
0108 /* MSTP13 */
0109 #define R7S72100_CLK_PIX1   2
0110 #define R7S72100_CLK_PIX0   1
0111
0112 #endif /* __DT_BINDINGS_CLOCK_R7S72100_H__ */