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0006 #ifndef _DT_BINDINGS_CLK_MSM_MMCC_8998_H
0007 #define _DT_BINDINGS_CLK_MSM_MMCC_8998_H
0008
0009 #define MMPLL0 0
0010 #define MMPLL0_OUT_EVEN 1
0011 #define MMPLL1 2
0012 #define MMPLL1_OUT_EVEN 3
0013 #define MMPLL3 4
0014 #define MMPLL3_OUT_EVEN 5
0015 #define MMPLL4 6
0016 #define MMPLL4_OUT_EVEN 7
0017 #define MMPLL5 8
0018 #define MMPLL5_OUT_EVEN 9
0019 #define MMPLL6 10
0020 #define MMPLL6_OUT_EVEN 11
0021 #define MMPLL7 12
0022 #define MMPLL7_OUT_EVEN 13
0023 #define MMPLL10 14
0024 #define MMPLL10_OUT_EVEN 15
0025 #define BYTE0_CLK_SRC 16
0026 #define BYTE1_CLK_SRC 17
0027 #define CCI_CLK_SRC 18
0028 #define CPP_CLK_SRC 19
0029 #define CSI0_CLK_SRC 20
0030 #define CSI1_CLK_SRC 21
0031 #define CSI2_CLK_SRC 22
0032 #define CSI3_CLK_SRC 23
0033 #define CSIPHY_CLK_SRC 24
0034 #define CSI0PHYTIMER_CLK_SRC 25
0035 #define CSI1PHYTIMER_CLK_SRC 26
0036 #define CSI2PHYTIMER_CLK_SRC 27
0037 #define DP_AUX_CLK_SRC 28
0038 #define DP_CRYPTO_CLK_SRC 29
0039 #define DP_LINK_CLK_SRC 30
0040 #define DP_PIXEL_CLK_SRC 31
0041 #define ESC0_CLK_SRC 32
0042 #define ESC1_CLK_SRC 33
0043 #define EXTPCLK_CLK_SRC 34
0044 #define FD_CORE_CLK_SRC 35
0045 #define HDMI_CLK_SRC 36
0046 #define JPEG0_CLK_SRC 37
0047 #define MAXI_CLK_SRC 38
0048 #define MCLK0_CLK_SRC 39
0049 #define MCLK1_CLK_SRC 40
0050 #define MCLK2_CLK_SRC 41
0051 #define MCLK3_CLK_SRC 42
0052 #define MDP_CLK_SRC 43
0053 #define VSYNC_CLK_SRC 44
0054 #define AHB_CLK_SRC 45
0055 #define AXI_CLK_SRC 46
0056 #define PCLK0_CLK_SRC 47
0057 #define PCLK1_CLK_SRC 48
0058 #define ROT_CLK_SRC 49
0059 #define VIDEO_CORE_CLK_SRC 50
0060 #define VIDEO_SUBCORE0_CLK_SRC 51
0061 #define VIDEO_SUBCORE1_CLK_SRC 52
0062 #define VFE0_CLK_SRC 53
0063 #define VFE1_CLK_SRC 54
0064 #define MISC_AHB_CLK 55
0065 #define VIDEO_CORE_CLK 56
0066 #define VIDEO_AHB_CLK 57
0067 #define VIDEO_AXI_CLK 58
0068 #define VIDEO_MAXI_CLK 59
0069 #define VIDEO_SUBCORE0_CLK 60
0070 #define VIDEO_SUBCORE1_CLK 61
0071 #define MDSS_AHB_CLK 62
0072 #define MDSS_HDMI_DP_AHB_CLK 63
0073 #define MDSS_AXI_CLK 64
0074 #define MDSS_PCLK0_CLK 65
0075 #define MDSS_PCLK1_CLK 66
0076 #define MDSS_MDP_CLK 67
0077 #define MDSS_MDP_LUT_CLK 68
0078 #define MDSS_EXTPCLK_CLK 69
0079 #define MDSS_VSYNC_CLK 70
0080 #define MDSS_HDMI_CLK 71
0081 #define MDSS_BYTE0_CLK 72
0082 #define MDSS_BYTE1_CLK 73
0083 #define MDSS_ESC0_CLK 74
0084 #define MDSS_ESC1_CLK 75
0085 #define MDSS_ROT_CLK 76
0086 #define MDSS_DP_LINK_CLK 77
0087 #define MDSS_DP_LINK_INTF_CLK 78
0088 #define MDSS_DP_CRYPTO_CLK 79
0089 #define MDSS_DP_PIXEL_CLK 80
0090 #define MDSS_DP_AUX_CLK 81
0091 #define MDSS_BYTE0_INTF_CLK 82
0092 #define MDSS_BYTE1_INTF_CLK 83
0093 #define CAMSS_CSI0PHYTIMER_CLK 84
0094 #define CAMSS_CSI1PHYTIMER_CLK 85
0095 #define CAMSS_CSI2PHYTIMER_CLK 86
0096 #define CAMSS_CSI0_CLK 87
0097 #define CAMSS_CSI0_AHB_CLK 88
0098 #define CAMSS_CSI0RDI_CLK 89
0099 #define CAMSS_CSI0PIX_CLK 90
0100 #define CAMSS_CSI1_CLK 91
0101 #define CAMSS_CSI1_AHB_CLK 92
0102 #define CAMSS_CSI1RDI_CLK 93
0103 #define CAMSS_CSI1PIX_CLK 94
0104 #define CAMSS_CSI2_CLK 95
0105 #define CAMSS_CSI2_AHB_CLK 96
0106 #define CAMSS_CSI2RDI_CLK 97
0107 #define CAMSS_CSI2PIX_CLK 98
0108 #define CAMSS_CSI3_CLK 99
0109 #define CAMSS_CSI3_AHB_CLK 100
0110 #define CAMSS_CSI3RDI_CLK 101
0111 #define CAMSS_CSI3PIX_CLK 102
0112 #define CAMSS_ISPIF_AHB_CLK 103
0113 #define CAMSS_CCI_CLK 104
0114 #define CAMSS_CCI_AHB_CLK 105
0115 #define CAMSS_MCLK0_CLK 106
0116 #define CAMSS_MCLK1_CLK 107
0117 #define CAMSS_MCLK2_CLK 108
0118 #define CAMSS_MCLK3_CLK 109
0119 #define CAMSS_TOP_AHB_CLK 110
0120 #define CAMSS_AHB_CLK 111
0121 #define CAMSS_MICRO_AHB_CLK 112
0122 #define CAMSS_JPEG0_CLK 113
0123 #define CAMSS_JPEG_AHB_CLK 114
0124 #define CAMSS_JPEG_AXI_CLK 115
0125 #define CAMSS_VFE0_AHB_CLK 116
0126 #define CAMSS_VFE1_AHB_CLK 117
0127 #define CAMSS_VFE0_CLK 118
0128 #define CAMSS_VFE1_CLK 119
0129 #define CAMSS_CPP_CLK 120
0130 #define CAMSS_CPP_AHB_CLK 121
0131 #define CAMSS_VFE_VBIF_AHB_CLK 122
0132 #define CAMSS_VFE_VBIF_AXI_CLK 123
0133 #define CAMSS_CPP_AXI_CLK 124
0134 #define CAMSS_CPP_VBIF_AHB_CLK 125
0135 #define CAMSS_CSI_VFE0_CLK 126
0136 #define CAMSS_CSI_VFE1_CLK 127
0137 #define CAMSS_VFE0_STREAM_CLK 128
0138 #define CAMSS_VFE1_STREAM_CLK 129
0139 #define CAMSS_CPHY_CSID0_CLK 130
0140 #define CAMSS_CPHY_CSID1_CLK 131
0141 #define CAMSS_CPHY_CSID2_CLK 132
0142 #define CAMSS_CPHY_CSID3_CLK 133
0143 #define CAMSS_CSIPHY0_CLK 134
0144 #define CAMSS_CSIPHY1_CLK 135
0145 #define CAMSS_CSIPHY2_CLK 136
0146 #define FD_CORE_CLK 137
0147 #define FD_CORE_UAR_CLK 138
0148 #define FD_AHB_CLK 139
0149 #define MNOC_AHB_CLK 140
0150 #define BIMC_SMMU_AHB_CLK 141
0151 #define BIMC_SMMU_AXI_CLK 142
0152 #define MNOC_MAXI_CLK 143
0153 #define VMEM_MAXI_CLK 144
0154 #define VMEM_AHB_CLK 145
0155
0156 #define SPDM_BCR 0
0157 #define SPDM_RM_BCR 1
0158 #define MISC_BCR 2
0159 #define VIDEO_TOP_BCR 3
0160 #define THROTTLE_VIDEO_BCR 4
0161 #define MDSS_BCR 5
0162 #define THROTTLE_MDSS_BCR 6
0163 #define CAMSS_PHY0_BCR 7
0164 #define CAMSS_PHY1_BCR 8
0165 #define CAMSS_PHY2_BCR 9
0166 #define CAMSS_CSI0_BCR 10
0167 #define CAMSS_CSI0RDI_BCR 11
0168 #define CAMSS_CSI0PIX_BCR 12
0169 #define CAMSS_CSI1_BCR 13
0170 #define CAMSS_CSI1RDI_BCR 14
0171 #define CAMSS_CSI1PIX_BCR 15
0172 #define CAMSS_CSI2_BCR 16
0173 #define CAMSS_CSI2RDI_BCR 17
0174 #define CAMSS_CSI2PIX_BCR 18
0175 #define CAMSS_CSI3_BCR 19
0176 #define CAMSS_CSI3RDI_BCR 20
0177 #define CAMSS_CSI3PIX_BCR 21
0178 #define CAMSS_ISPIF_BCR 22
0179 #define CAMSS_CCI_BCR 23
0180 #define CAMSS_TOP_BCR 24
0181 #define CAMSS_AHB_BCR 25
0182 #define CAMSS_MICRO_BCR 26
0183 #define CAMSS_JPEG_BCR 27
0184 #define CAMSS_VFE0_BCR 28
0185 #define CAMSS_VFE1_BCR 29
0186 #define CAMSS_VFE_VBIF_BCR 30
0187 #define CAMSS_CPP_TOP_BCR 31
0188 #define CAMSS_CPP_BCR 32
0189 #define CAMSS_CSI_VFE0_BCR 33
0190 #define CAMSS_CSI_VFE1_BCR 34
0191 #define CAMSS_FD_BCR 35
0192 #define THROTTLE_CAMSS_BCR 36
0193 #define MNOCAHB_BCR 37
0194 #define MNOCAXI_BCR 38
0195 #define BMIC_SMMU_BCR 39
0196 #define MNOC_MAXI_BCR 40
0197 #define VMEM_BCR 41
0198 #define BTO_BCR 42
0199
0200 #define VIDEO_TOP_GDSC 1
0201 #define VIDEO_SUBCORE0_GDSC 2
0202 #define VIDEO_SUBCORE1_GDSC 3
0203 #define MDSS_GDSC 4
0204 #define CAMSS_TOP_GDSC 5
0205 #define CAMSS_VFE0_GDSC 6
0206 #define CAMSS_VFE1_GDSC 7
0207 #define CAMSS_CPP_GDSC 8
0208 #define BIMC_SMMU_GDSC 9
0209
0210 #endif