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OSCL-LXR

 
 

    


0001 /*
0002  * Copyright (c) 2015 Joachim Eastwood <manabian@gmail.com>
0003  *
0004  * This code is released using a dual license strategy: BSD/GPL
0005  * You can choose the licence that better fits your requirements.
0006  *
0007  * Released under the terms of 3-clause BSD License
0008  * Released under the terms of GNU General Public License Version 2.0
0009  *
0010  */
0011 
0012 /* LPC18xx/43xx base clock ids */
0013 #define BASE_SAFE_CLK       0
0014 #define BASE_USB0_CLK       1
0015 #define BASE_PERIPH_CLK     2
0016 #define BASE_USB1_CLK       3
0017 #define BASE_CPU_CLK        4
0018 #define BASE_SPIFI_CLK      5
0019 #define BASE_SPI_CLK        6
0020 #define BASE_PHY_RX_CLK     7
0021 #define BASE_PHY_TX_CLK     8
0022 #define BASE_APB1_CLK       9
0023 #define BASE_APB3_CLK       10
0024 #define BASE_LCD_CLK        11
0025 #define BASE_ADCHS_CLK      12
0026 #define BASE_SDIO_CLK       13
0027 #define BASE_SSP0_CLK       14
0028 #define BASE_SSP1_CLK       15
0029 #define BASE_UART0_CLK      16
0030 #define BASE_UART1_CLK      17
0031 #define BASE_UART2_CLK      18
0032 #define BASE_UART3_CLK      19
0033 #define BASE_OUT_CLK        20
0034 #define BASE_RES1_CLK       21
0035 #define BASE_RES2_CLK       22
0036 #define BASE_RES3_CLK       23
0037 #define BASE_RES4_CLK       24
0038 #define BASE_AUDIO_CLK      25
0039 #define BASE_CGU_OUT0_CLK   26
0040 #define BASE_CGU_OUT1_CLK   27
0041 #define BASE_CLK_MAX        (BASE_CGU_OUT1_CLK + 1)