dt-bindings/clock/hi3620-clock.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright (c) 2012-2013 Hisilicon Limited.
0004  * Copyright (c) 2012-2013 Linaro Limited.
0005  *
0006  * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
0007  *     Xin Li <li.xin@linaro.org>
0008  */
0009
0010 #ifndef __DTS_HI3620_CLOCK_H
0011 #define __DTS_HI3620_CLOCK_H
0012
0013 #define HI3620_NONE_CLOCK   0
0014
0015 /* fixed rate & fixed factor clocks */
0016 #define HI3620_OSC32K       1
0017 #define HI3620_OSC26M       2
0018 #define HI3620_PCLK     3
0019 #define HI3620_PLL_ARM0     4
0020 #define HI3620_PLL_ARM1     5
0021 #define HI3620_PLL_PERI     6
0022 #define HI3620_PLL_USB      7
0023 #define HI3620_PLL_HDMI     8
0024 #define HI3620_PLL_GPU      9
0025 #define HI3620_RCLK_TCXO    10
0026 #define HI3620_RCLK_CFGAXI  11
0027 #define HI3620_RCLK_PICO    12
0028
0029 /* mux clocks */
0030 #define HI3620_TIMER0_MUX   32
0031 #define HI3620_TIMER1_MUX   33
0032 #define HI3620_TIMER2_MUX   34
0033 #define HI3620_TIMER3_MUX   35
0034 #define HI3620_TIMER4_MUX   36
0035 #define HI3620_TIMER5_MUX   37
0036 #define HI3620_TIMER6_MUX   38
0037 #define HI3620_TIMER7_MUX   39
0038 #define HI3620_TIMER8_MUX   40
0039 #define HI3620_TIMER9_MUX   41
0040 #define HI3620_UART0_MUX    42
0041 #define HI3620_UART1_MUX    43
0042 #define HI3620_UART2_MUX    44
0043 #define HI3620_UART3_MUX    45
0044 #define HI3620_UART4_MUX    46
0045 #define HI3620_SPI0_MUX     47
0046 #define HI3620_SPI1_MUX     48
0047 #define HI3620_SPI2_MUX     49
0048 #define HI3620_SAXI_MUX     50
0049 #define HI3620_PWM0_MUX     51
0050 #define HI3620_PWM1_MUX     52
0051 #define HI3620_SD_MUX       53
0052 #define HI3620_MMC1_MUX     54
0053 #define HI3620_MMC1_MUX2    55
0054 #define HI3620_G2D_MUX      56
0055 #define HI3620_VENC_MUX     57
0056 #define HI3620_VDEC_MUX     58
0057 #define HI3620_VPP_MUX      59
0058 #define HI3620_EDC0_MUX     60
0059 #define HI3620_LDI0_MUX     61
0060 #define HI3620_EDC1_MUX     62
0061 #define HI3620_LDI1_MUX     63
0062 #define HI3620_RCLK_HSIC    64
0063 #define HI3620_MMC2_MUX     65
0064 #define HI3620_MMC3_MUX     66
0065
0066 /* divider clocks */
0067 #define HI3620_SHAREAXI_DIV 128
0068 #define HI3620_CFGAXI_DIV   129
0069 #define HI3620_SD_DIV       130
0070 #define HI3620_MMC1_DIV     131
0071 #define HI3620_HSIC_DIV     132
0072 #define HI3620_MMC2_DIV     133
0073 #define HI3620_MMC3_DIV     134
0074
0075 /* gate clocks */
0076 #define HI3620_TIMERCLK01   160
0077 #define HI3620_TIMER_RCLK01 161
0078 #define HI3620_TIMERCLK23   162
0079 #define HI3620_TIMER_RCLK23 163
0080 #define HI3620_TIMERCLK45   164
0081 #define HI3620_TIMERCLK67   165
0082 #define HI3620_TIMERCLK89   166
0083 #define HI3620_RTCCLK       167
0084 #define HI3620_KPC_CLK      168
0085 #define HI3620_GPIOCLK0     169
0086 #define HI3620_GPIOCLK1     170
0087 #define HI3620_GPIOCLK2     171
0088 #define HI3620_GPIOCLK3     172
0089 #define HI3620_GPIOCLK4     173
0090 #define HI3620_GPIOCLK5     174
0091 #define HI3620_GPIOCLK6     175
0092 #define HI3620_GPIOCLK7     176
0093 #define HI3620_GPIOCLK8     177
0094 #define HI3620_GPIOCLK9     178
0095 #define HI3620_GPIOCLK10    179
0096 #define HI3620_GPIOCLK11    180
0097 #define HI3620_GPIOCLK12    181
0098 #define HI3620_GPIOCLK13    182
0099 #define HI3620_GPIOCLK14    183
0100 #define HI3620_GPIOCLK15    184
0101 #define HI3620_GPIOCLK16    185
0102 #define HI3620_GPIOCLK17    186
0103 #define HI3620_GPIOCLK18    187
0104 #define HI3620_GPIOCLK19    188
0105 #define HI3620_GPIOCLK20    189
0106 #define HI3620_GPIOCLK21    190
0107 #define HI3620_DPHY0_CLK    191
0108 #define HI3620_DPHY1_CLK    192
0109 #define HI3620_DPHY2_CLK    193
0110 #define HI3620_USBPHY_CLK   194
0111 #define HI3620_ACP_CLK      195
0112 #define HI3620_PWMCLK0      196
0113 #define HI3620_PWMCLK1      197
0114 #define HI3620_UARTCLK0     198
0115 #define HI3620_UARTCLK1     199
0116 #define HI3620_UARTCLK2     200
0117 #define HI3620_UARTCLK3     201
0118 #define HI3620_UARTCLK4     202
0119 #define HI3620_SPICLK0      203
0120 #define HI3620_SPICLK1      204
0121 #define HI3620_SPICLK2      205
0122 #define HI3620_I2CCLK0      206
0123 #define HI3620_I2CCLK1      207
0124 #define HI3620_I2CCLK2      208
0125 #define HI3620_I2CCLK3      209
0126 #define HI3620_SCI_CLK      210
0127 #define HI3620_DDRC_PER_CLK 211
0128 #define HI3620_DMAC_CLK     212
0129 #define HI3620_USB2DVC_CLK  213
0130 #define HI3620_SD_CLK       214
0131 #define HI3620_MMC_CLK1     215
0132 #define HI3620_MMC_CLK2     216
0133 #define HI3620_MMC_CLK3     217
0134 #define HI3620_MCU_CLK      218
0135
0136 #define HI3620_SD_CIUCLK    0
0137 #define HI3620_MMC_CIUCLK1  1
0138 #define HI3620_MMC_CIUCLK2  2
0139 #define HI3620_MMC_CIUCLK3  3
0140
0141 #define HI3620_NR_CLKS      219
0142
0143 #endif  /* __DTS_HI3620_CLOCK_H */