dt-bindings/clock/bt1-ccu.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
0004  *
0005  * Baikal-T1 CCU clock indices
0006  */
0007 #ifndef __DT_BINDINGS_CLOCK_BT1_CCU_H
0008 #define __DT_BINDINGS_CLOCK_BT1_CCU_H
0009
0010 #define CCU_CPU_PLL         0
0011 #define CCU_SATA_PLL            1
0012 #define CCU_DDR_PLL         2
0013 #define CCU_PCIE_PLL            3
0014 #define CCU_ETH_PLL         4
0015
0016 #define CCU_AXI_MAIN_CLK        0
0017 #define CCU_AXI_DDR_CLK         1
0018 #define CCU_AXI_SATA_CLK        2
0019 #define CCU_AXI_GMAC0_CLK       3
0020 #define CCU_AXI_GMAC1_CLK       4
0021 #define CCU_AXI_XGMAC_CLK       5
0022 #define CCU_AXI_PCIE_M_CLK      6
0023 #define CCU_AXI_PCIE_S_CLK      7
0024 #define CCU_AXI_USB_CLK         8
0025 #define CCU_AXI_HWA_CLK         9
0026 #define CCU_AXI_SRAM_CLK        10
0027
0028 #define CCU_SYS_SATA_REF_CLK        0
0029 #define CCU_SYS_APB_CLK         1
0030 #define CCU_SYS_GMAC0_TX_CLK        2
0031 #define CCU_SYS_GMAC0_PTP_CLK       3
0032 #define CCU_SYS_GMAC1_TX_CLK        4
0033 #define CCU_SYS_GMAC1_PTP_CLK       5
0034 #define CCU_SYS_XGMAC_REF_CLK       6
0035 #define CCU_SYS_XGMAC_PTP_CLK       7
0036 #define CCU_SYS_USB_CLK         8
0037 #define CCU_SYS_PVT_CLK         9
0038 #define CCU_SYS_HWA_CLK         10
0039 #define CCU_SYS_UART_CLK        11
0040 #define CCU_SYS_I2C1_CLK        12
0041 #define CCU_SYS_I2C2_CLK        13
0042 #define CCU_SYS_GPIO_CLK        14
0043 #define CCU_SYS_TIMER0_CLK      15
0044 #define CCU_SYS_TIMER1_CLK      16
0045 #define CCU_SYS_TIMER2_CLK      17
0046 #define CCU_SYS_WDT_CLK         18
0047
0048 #endif /* __DT_BINDINGS_CLOCK_BT1_CCU_H */