dt-bindings/clock/bm1880-clock.h

0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 /*
0003  * Device Tree binding constants for Bitmain BM1880 SoC
0004  *
0005  * Copyright (c) 2019 Linaro Ltd.
0006  */
0007
0008 #ifndef __DT_BINDINGS_CLOCK_BM1880_H
0009 #define __DT_BINDINGS_CLOCK_BM1880_H
0010
0011 #define BM1880_CLK_OSC          0
0012 #define BM1880_CLK_MPLL         1
0013 #define BM1880_CLK_SPLL         2
0014 #define BM1880_CLK_FPLL         3
0015 #define BM1880_CLK_DDRPLL       4
0016 #define BM1880_CLK_A53          5
0017 #define BM1880_CLK_50M_A53      6
0018 #define BM1880_CLK_AHB_ROM      7
0019 #define BM1880_CLK_AXI_SRAM     8
0020 #define BM1880_CLK_DDR_AXI      9
0021 #define BM1880_CLK_EFUSE        10
0022 #define BM1880_CLK_APB_EFUSE        11
0023 #define BM1880_CLK_AXI5_EMMC        12
0024 #define BM1880_CLK_EMMC         13
0025 #define BM1880_CLK_100K_EMMC        14
0026 #define BM1880_CLK_AXI5_SD      15
0027 #define BM1880_CLK_SD           16
0028 #define BM1880_CLK_100K_SD      17
0029 #define BM1880_CLK_500M_ETH0        18
0030 #define BM1880_CLK_AXI4_ETH0        19
0031 #define BM1880_CLK_500M_ETH1        20
0032 #define BM1880_CLK_AXI4_ETH1        21
0033 #define BM1880_CLK_AXI1_GDMA        22
0034 #define BM1880_CLK_APB_GPIO     23
0035 #define BM1880_CLK_APB_GPIO_INTR    24
0036 #define BM1880_CLK_GPIO_DB      25
0037 #define BM1880_CLK_AXI1_MINER       26
0038 #define BM1880_CLK_AHB_SF       27
0039 #define BM1880_CLK_SDMA_AXI     28
0040 #define BM1880_CLK_SDMA_AUD     29
0041 #define BM1880_CLK_APB_I2C      30
0042 #define BM1880_CLK_APB_WDT      31
0043 #define BM1880_CLK_APB_JPEG     32
0044 #define BM1880_CLK_JPEG_AXI     33
0045 #define BM1880_CLK_AXI5_NF      34
0046 #define BM1880_CLK_APB_NF       35
0047 #define BM1880_CLK_NF           36
0048 #define BM1880_CLK_APB_PWM      37
0049 #define BM1880_CLK_DIV_0_RV     38
0050 #define BM1880_CLK_DIV_1_RV     39
0051 #define BM1880_CLK_MUX_RV       40
0052 #define BM1880_CLK_RV           41
0053 #define BM1880_CLK_APB_SPI      42
0054 #define BM1880_CLK_TPU_AXI      43
0055 #define BM1880_CLK_DIV_UART_500M    44
0056 #define BM1880_CLK_UART_500M        45
0057 #define BM1880_CLK_APB_UART     46
0058 #define BM1880_CLK_APB_I2S      47
0059 #define BM1880_CLK_AXI4_USB     48
0060 #define BM1880_CLK_APB_USB      49
0061 #define BM1880_CLK_125M_USB     50
0062 #define BM1880_CLK_33K_USB      51
0063 #define BM1880_CLK_DIV_12M_USB      52
0064 #define BM1880_CLK_12M_USB      53
0065 #define BM1880_CLK_APB_VIDEO        54
0066 #define BM1880_CLK_VIDEO_AXI        55
0067 #define BM1880_CLK_VPP_AXI      56
0068 #define BM1880_CLK_APB_VPP      57
0069 #define BM1880_CLK_DIV_0_AXI1       58
0070 #define BM1880_CLK_DIV_1_AXI1       59
0071 #define BM1880_CLK_AXI1         60
0072 #define BM1880_CLK_AXI2         61
0073 #define BM1880_CLK_AXI3         62
0074 #define BM1880_CLK_AXI4         63
0075 #define BM1880_CLK_AXI5         64
0076 #define BM1880_CLK_DIV_0_AXI6       65
0077 #define BM1880_CLK_DIV_1_AXI6       66
0078 #define BM1880_CLK_MUX_AXI6     67
0079 #define BM1880_CLK_AXI6         68
0080 #define BM1880_NR_CLKS          69
0081
0082 #endif /* __DT_BINDINGS_CLOCK_BM1880_H */