dt-bindings/clock/bcm-sr.h

0001 /*
0002  *  BSD LICENSE
0003  *
0004  *  Copyright(c) 2017 Broadcom. All rights reserved.
0005  *
0006  *  Redistribution and use in source and binary forms, with or without
0007  *  modification, are permitted provided that the following conditions
0008  *  are met:
0009  *
0010  *    * Redistributions of source code must retain the above copyright
0011  *      notice, this list of conditions and the following disclaimer.
0012  *    * Redistributions in binary form must reproduce the above copyright
0013  *      notice, this list of conditions and the following disclaimer in
0014  *      the documentation and/or other materials provided with the
0015  *      distribution.
0016  *    * Neither the name of Broadcom Corporation nor the names of its
0017  *      contributors may be used to endorse or promote products derived
0018  *      from this software without specific prior written permission.
0019  *
0020  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
0021  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
0022  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
0023  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
0024  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
0025  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
0026  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
0027  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
0028  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0029  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
0030  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0031  */
0032
0033 #ifndef _CLOCK_BCM_SR_H
0034 #define _CLOCK_BCM_SR_H
0035
0036 /* GENPLL 0 clock channel ID SCR HSLS FS PCIE */
0037 #define BCM_SR_GENPLL0          0
0038 #define BCM_SR_GENPLL0_125M_CLK     1
0039 #define BCM_SR_GENPLL0_SCR_CLK      2
0040 #define BCM_SR_GENPLL0_250M_CLK     3
0041 #define BCM_SR_GENPLL0_PCIE_AXI_CLK 4
0042 #define BCM_SR_GENPLL0_PAXC_AXI_X2_CLK  5
0043 #define BCM_SR_GENPLL0_PAXC_AXI_CLK 6
0044
0045 /* GENPLL 1 clock channel ID MHB PCIE NITRO */
0046 #define BCM_SR_GENPLL1          0
0047 #define BCM_SR_GENPLL1_PCIE_TL_CLK  1
0048 #define BCM_SR_GENPLL1_MHB_APB_CLK  2
0049
0050 /* GENPLL 2 clock channel ID NITRO MHB*/
0051 #define BCM_SR_GENPLL2          0
0052 #define BCM_SR_GENPLL2_NIC_CLK      1
0053 #define BCM_SR_GENPLL2_TS_500_CLK   2
0054 #define BCM_SR_GENPLL2_125_NITRO_CLK    3
0055 #define BCM_SR_GENPLL2_CHIMP_CLK    4
0056 #define BCM_SR_GENPLL2_NIC_FLASH_CLK    5
0057 #define BCM_SR_GENPLL2_FS4_CLK      6
0058
0059 /* GENPLL 3 HSLS clock channel ID */
0060 #define BCM_SR_GENPLL3          0
0061 #define BCM_SR_GENPLL3_HSLS_CLK     1
0062 #define BCM_SR_GENPLL3_SDIO_CLK     2
0063
0064 /* GENPLL 4 SCR clock channel ID */
0065 #define BCM_SR_GENPLL4          0
0066 #define BCM_SR_GENPLL4_CCN_CLK      1
0067 #define BCM_SR_GENPLL4_TPIU_PLL_CLK 2
0068 #define BCM_SR_GENPLL4_NOC_CLK      3
0069 #define BCM_SR_GENPLL4_CHCLK_FS4_CLK    4
0070 #define BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK 5
0071
0072 /* GENPLL 5 FS4 clock channel ID */
0073 #define BCM_SR_GENPLL5          0
0074 #define BCM_SR_GENPLL5_FS4_HF_CLK   1
0075 #define BCM_SR_GENPLL5_CRYPTO_AE_CLK    2
0076 #define BCM_SR_GENPLL5_RAID_AE_CLK  3
0077
0078 /* GENPLL 6 NITRO clock channel ID */
0079 #define BCM_SR_GENPLL6          0
0080 #define BCM_SR_GENPLL6_48_USB_CLK   1
0081
0082 /* LCPLL0  clock channel ID */
0083 #define BCM_SR_LCPLL0           0
0084 #define BCM_SR_LCPLL0_SATA_REFP_CLK 1
0085 #define BCM_SR_LCPLL0_SATA_REFN_CLK 2
0086 #define BCM_SR_LCPLL0_SATA_350_CLK  3
0087 #define BCM_SR_LCPLL0_SATA_500_CLK  4
0088
0089 /* LCPLL1  clock channel ID */
0090 #define BCM_SR_LCPLL1           0
0091 #define BCM_SR_LCPLL1_WAN_CLK       1
0092 #define BCM_SR_LCPLL1_USB_REF_CLK   2
0093 #define BCM_SR_LCPLL1_CRMU_TS_CLK   3
0094
0095 /* LCPLL PCIE  clock channel ID */
0096 #define BCM_SR_LCPLL_PCIE       0
0097 #define BCM_SR_LCPLL_PCIE_PHY_REF_CLK   1
0098
0099 /* GENPLL EMEM0 clock channel ID */
0100 #define BCM_SR_EMEMPLL0         0
0101 #define BCM_SR_EMEMPLL0_EMEM_CLK    1
0102
0103 /* GENPLL EMEM0 clock channel ID */
0104 #define BCM_SR_EMEMPLL1         0
0105 #define BCM_SR_EMEMPLL1_EMEM_CLK    1
0106
0107 /* GENPLL EMEM0 clock channel ID */
0108 #define BCM_SR_EMEMPLL2         0
0109 #define BCM_SR_EMEMPLL2_EMEM_CLK    1
0110
0111 #endif /* _CLOCK_BCM_SR_H */