dt-bindings/clock/axg-clkc.h

0001 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
0002 /*
0003  * Meson-AXG clock tree IDs
0004  *
0005  * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
0006  */
0007
0008 #ifndef __AXG_CLKC_H
0009 #define __AXG_CLKC_H
0010
0011 #define CLKID_SYS_PLL               0
0012 #define CLKID_FIXED_PLL             1
0013 #define CLKID_FCLK_DIV2             2
0014 #define CLKID_FCLK_DIV3             3
0015 #define CLKID_FCLK_DIV4             4
0016 #define CLKID_FCLK_DIV5             5
0017 #define CLKID_FCLK_DIV7             6
0018 #define CLKID_GP0_PLL               7
0019 #define CLKID_CLK81             10
0020 #define CLKID_MPLL0             11
0021 #define CLKID_MPLL1             12
0022 #define CLKID_MPLL2             13
0023 #define CLKID_MPLL3             14
0024 #define CLKID_DDR               15
0025 #define CLKID_AUDIO_LOCKER          16
0026 #define CLKID_MIPI_DSI_HOST         17
0027 #define CLKID_ISA               18
0028 #define CLKID_PL301             19
0029 #define CLKID_PERIPHS               20
0030 #define CLKID_SPICC0                21
0031 #define CLKID_I2C               22
0032 #define CLKID_RNG0              23
0033 #define CLKID_UART0             24
0034 #define CLKID_MIPI_DSI_PHY          25
0035 #define CLKID_SPICC1                26
0036 #define CLKID_PCIE_A                27
0037 #define CLKID_PCIE_B                28
0038 #define CLKID_HIU_IFACE             29
0039 #define CLKID_ASSIST_MISC           30
0040 #define CLKID_SD_EMMC_B             31
0041 #define CLKID_SD_EMMC_C             32
0042 #define CLKID_DMA               33
0043 #define CLKID_SPI               34
0044 #define CLKID_AUDIO             35
0045 #define CLKID_ETH               36
0046 #define CLKID_UART1             37
0047 #define CLKID_G2D               38
0048 #define CLKID_USB0              39
0049 #define CLKID_USB1              40
0050 #define CLKID_RESET             41
0051 #define CLKID_USB               42
0052 #define CLKID_AHB_ARB0              43
0053 #define CLKID_EFUSE             44
0054 #define CLKID_BOOT_ROM              45
0055 #define CLKID_AHB_DATA_BUS          46
0056 #define CLKID_AHB_CTRL_BUS          47
0057 #define CLKID_USB1_DDR_BRIDGE           48
0058 #define CLKID_USB0_DDR_BRIDGE           49
0059 #define CLKID_MMC_PCLK              50
0060 #define CLKID_VPU_INTR              51
0061 #define CLKID_SEC_AHB_AHB3_BRIDGE       52
0062 #define CLKID_GIC               53
0063 #define CLKID_AO_MEDIA_CPU          54
0064 #define CLKID_AO_AHB_SRAM           55
0065 #define CLKID_AO_AHB_BUS            56
0066 #define CLKID_AO_IFACE              57
0067 #define CLKID_AO_I2C                58
0068 #define CLKID_SD_EMMC_B_CLK0            59
0069 #define CLKID_SD_EMMC_C_CLK0            60
0070 #define CLKID_HIFI_PLL              69
0071 #define CLKID_PCIE_CML_EN0          79
0072 #define CLKID_PCIE_CML_EN1          80
0073 #define CLKID_GEN_CLK               84
0074 #define CLKID_VPU_0_SEL             92
0075 #define CLKID_VPU_0             93
0076 #define CLKID_VPU_1_SEL             95
0077 #define CLKID_VPU_1             96
0078 #define CLKID_VPU               97
0079 #define CLKID_VAPB_0_SEL            99
0080 #define CLKID_VAPB_0                100
0081 #define CLKID_VAPB_1_SEL            102
0082 #define CLKID_VAPB_1                103
0083 #define CLKID_VAPB_SEL              104
0084 #define CLKID_VAPB              105
0085 #define CLKID_VCLK              106
0086 #define CLKID_VCLK2             107
0087 #define CLKID_VCLK_DIV1             122
0088 #define CLKID_VCLK_DIV2             123
0089 #define CLKID_VCLK_DIV4             124
0090 #define CLKID_VCLK_DIV6             125
0091 #define CLKID_VCLK_DIV12            126
0092 #define CLKID_VCLK2_DIV1            127
0093 #define CLKID_VCLK2_DIV2            128
0094 #define CLKID_VCLK2_DIV4            129
0095 #define CLKID_VCLK2_DIV6            130
0096 #define CLKID_VCLK2_DIV12           131
0097 #define CLKID_CTS_ENCL              133
0098 #define CLKID_VDIN_MEAS             136
0099
0100 #endif /* __AXG_CLKC_H */