0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003 * dts file for Xilinx ZynqMP
0004 *
0005 * (C) Copyright 2014 - 2021, Xilinx, Inc.
0006 *
0007 * Michal Simek <michal.simek@xilinx.com>
0008 *
0009 * This program is free software; you can redistribute it and/or
0010 * modify it under the terms of the GNU General Public License as
0011 * published by the Free Software Foundation; either version 2 of
0012 * the License, or (at your option) any later version.
0013 */
0014
0015 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
0016 #include <dt-bindings/power/xlnx-zynqmp-power.h>
0017 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
0018
0019 / {
0020 compatible = "xlnx,zynqmp";
0021 #address-cells = <2>;
0022 #size-cells = <2>;
0023
0024 cpus {
0025 #address-cells = <1>;
0026 #size-cells = <0>;
0027
0028 cpu0: cpu@0 {
0029 compatible = "arm,cortex-a53";
0030 device_type = "cpu";
0031 enable-method = "psci";
0032 operating-points-v2 = <&cpu_opp_table>;
0033 reg = <0x0>;
0034 cpu-idle-states = <&CPU_SLEEP_0>;
0035 };
0036
0037 cpu1: cpu@1 {
0038 compatible = "arm,cortex-a53";
0039 device_type = "cpu";
0040 enable-method = "psci";
0041 reg = <0x1>;
0042 operating-points-v2 = <&cpu_opp_table>;
0043 cpu-idle-states = <&CPU_SLEEP_0>;
0044 };
0045
0046 cpu2: cpu@2 {
0047 compatible = "arm,cortex-a53";
0048 device_type = "cpu";
0049 enable-method = "psci";
0050 reg = <0x2>;
0051 operating-points-v2 = <&cpu_opp_table>;
0052 cpu-idle-states = <&CPU_SLEEP_0>;
0053 };
0054
0055 cpu3: cpu@3 {
0056 compatible = "arm,cortex-a53";
0057 device_type = "cpu";
0058 enable-method = "psci";
0059 reg = <0x3>;
0060 operating-points-v2 = <&cpu_opp_table>;
0061 cpu-idle-states = <&CPU_SLEEP_0>;
0062 };
0063
0064 idle-states {
0065 entry-method = "psci";
0066
0067 CPU_SLEEP_0: cpu-sleep-0 {
0068 compatible = "arm,idle-state";
0069 arm,psci-suspend-param = <0x40000000>;
0070 local-timer-stop;
0071 entry-latency-us = <300>;
0072 exit-latency-us = <600>;
0073 min-residency-us = <10000>;
0074 };
0075 };
0076 };
0077
0078 cpu_opp_table: cpu-opp-table {
0079 compatible = "operating-points-v2";
0080 opp-shared;
0081 opp00 {
0082 opp-hz = /bits/ 64 <1199999988>;
0083 opp-microvolt = <1000000>;
0084 clock-latency-ns = <500000>;
0085 };
0086 opp01 {
0087 opp-hz = /bits/ 64 <599999994>;
0088 opp-microvolt = <1000000>;
0089 clock-latency-ns = <500000>;
0090 };
0091 opp02 {
0092 opp-hz = /bits/ 64 <399999996>;
0093 opp-microvolt = <1000000>;
0094 clock-latency-ns = <500000>;
0095 };
0096 opp03 {
0097 opp-hz = /bits/ 64 <299999997>;
0098 opp-microvolt = <1000000>;
0099 clock-latency-ns = <500000>;
0100 };
0101 };
0102
0103 zynqmp_ipi: zynqmp_ipi {
0104 compatible = "xlnx,zynqmp-ipi-mailbox";
0105 interrupt-parent = <&gic>;
0106 interrupts = <0 35 4>;
0107 xlnx,ipi-id = <0>;
0108 #address-cells = <2>;
0109 #size-cells = <2>;
0110 ranges;
0111
0112 ipi_mailbox_pmu1: mailbox@ff990400 {
0113 reg = <0x0 0xff9905c0 0x0 0x20>,
0114 <0x0 0xff9905e0 0x0 0x20>,
0115 <0x0 0xff990e80 0x0 0x20>,
0116 <0x0 0xff990ea0 0x0 0x20>;
0117 reg-names = "local_request_region",
0118 "local_response_region",
0119 "remote_request_region",
0120 "remote_response_region";
0121 #mbox-cells = <1>;
0122 xlnx,ipi-id = <4>;
0123 };
0124 };
0125
0126 dcc: dcc {
0127 compatible = "arm,dcc";
0128 status = "disabled";
0129 };
0130
0131 pmu {
0132 compatible = "arm,armv8-pmuv3";
0133 interrupt-parent = <&gic>;
0134 interrupts = <0 143 4>,
0135 <0 144 4>,
0136 <0 145 4>,
0137 <0 146 4>;
0138 };
0139
0140 psci {
0141 compatible = "arm,psci-0.2";
0142 method = "smc";
0143 };
0144
0145 firmware {
0146 zynqmp_firmware: zynqmp-firmware {
0147 compatible = "xlnx,zynqmp-firmware";
0148 #power-domain-cells = <1>;
0149 method = "smc";
0150
0151 zynqmp_power: zynqmp-power {
0152 compatible = "xlnx,zynqmp-power";
0153 interrupt-parent = <&gic>;
0154 interrupts = <0 35 4>;
0155 mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>;
0156 mbox-names = "tx", "rx";
0157 };
0158
0159 nvmem_firmware {
0160 compatible = "xlnx,zynqmp-nvmem-fw";
0161 #address-cells = <1>;
0162 #size-cells = <1>;
0163
0164 soc_revision: soc_revision@0 {
0165 reg = <0x0 0x4>;
0166 };
0167 };
0168
0169 zynqmp_pcap: pcap {
0170 compatible = "xlnx,zynqmp-pcap-fpga";
0171 };
0172
0173 xlnx_aes: zynqmp-aes {
0174 compatible = "xlnx,zynqmp-aes";
0175 };
0176
0177 zynqmp_reset: reset-controller {
0178 compatible = "xlnx,zynqmp-reset";
0179 #reset-cells = <1>;
0180 };
0181
0182 pinctrl0: pinctrl {
0183 compatible = "xlnx,zynqmp-pinctrl";
0184 status = "disabled";
0185 };
0186 };
0187 };
0188
0189 timer {
0190 compatible = "arm,armv8-timer";
0191 interrupt-parent = <&gic>;
0192 interrupts = <1 13 0xf08>,
0193 <1 14 0xf08>,
0194 <1 11 0xf08>,
0195 <1 10 0xf08>;
0196 };
0197
0198 fpga_full: fpga-full {
0199 compatible = "fpga-region";
0200 fpga-mgr = <&zynqmp_pcap>;
0201 #address-cells = <2>;
0202 #size-cells = <2>;
0203 ranges;
0204 };
0205
0206 amba: axi {
0207 compatible = "simple-bus";
0208 #address-cells = <2>;
0209 #size-cells = <2>;
0210 ranges;
0211
0212 can0: can@ff060000 {
0213 compatible = "xlnx,zynq-can-1.0";
0214 status = "disabled";
0215 clock-names = "can_clk", "pclk";
0216 reg = <0x0 0xff060000 0x0 0x1000>;
0217 interrupts = <0 23 4>;
0218 interrupt-parent = <&gic>;
0219 tx-fifo-depth = <0x40>;
0220 rx-fifo-depth = <0x40>;
0221 power-domains = <&zynqmp_firmware PD_CAN_0>;
0222 };
0223
0224 can1: can@ff070000 {
0225 compatible = "xlnx,zynq-can-1.0";
0226 status = "disabled";
0227 clock-names = "can_clk", "pclk";
0228 reg = <0x0 0xff070000 0x0 0x1000>;
0229 interrupts = <0 24 4>;
0230 interrupt-parent = <&gic>;
0231 tx-fifo-depth = <0x40>;
0232 rx-fifo-depth = <0x40>;
0233 power-domains = <&zynqmp_firmware PD_CAN_1>;
0234 };
0235
0236 cci: cci@fd6e0000 {
0237 compatible = "arm,cci-400";
0238 status = "disabled";
0239 reg = <0x0 0xfd6e0000 0x0 0x9000>;
0240 ranges = <0x0 0x0 0xfd6e0000 0x10000>;
0241 #address-cells = <1>;
0242 #size-cells = <1>;
0243
0244 pmu@9000 {
0245 compatible = "arm,cci-400-pmu,r1";
0246 reg = <0x9000 0x5000>;
0247 interrupt-parent = <&gic>;
0248 interrupts = <0 123 4>,
0249 <0 123 4>,
0250 <0 123 4>,
0251 <0 123 4>,
0252 <0 123 4>;
0253 };
0254 };
0255
0256 /* GDMA */
0257 fpd_dma_chan1: dma-controller@fd500000 {
0258 status = "disabled";
0259 compatible = "xlnx,zynqmp-dma-1.0";
0260 reg = <0x0 0xfd500000 0x0 0x1000>;
0261 interrupt-parent = <&gic>;
0262 interrupts = <0 124 4>;
0263 clock-names = "clk_main", "clk_apb";
0264 #dma-cells = <1>;
0265 xlnx,bus-width = <128>;
0266 iommus = <&smmu 0x14e8>;
0267 power-domains = <&zynqmp_firmware PD_GDMA>;
0268 };
0269
0270 fpd_dma_chan2: dma-controller@fd510000 {
0271 status = "disabled";
0272 compatible = "xlnx,zynqmp-dma-1.0";
0273 reg = <0x0 0xfd510000 0x0 0x1000>;
0274 interrupt-parent = <&gic>;
0275 interrupts = <0 125 4>;
0276 clock-names = "clk_main", "clk_apb";
0277 #dma-cells = <1>;
0278 xlnx,bus-width = <128>;
0279 iommus = <&smmu 0x14e9>;
0280 power-domains = <&zynqmp_firmware PD_GDMA>;
0281 };
0282
0283 fpd_dma_chan3: dma-controller@fd520000 {
0284 status = "disabled";
0285 compatible = "xlnx,zynqmp-dma-1.0";
0286 reg = <0x0 0xfd520000 0x0 0x1000>;
0287 interrupt-parent = <&gic>;
0288 interrupts = <0 126 4>;
0289 clock-names = "clk_main", "clk_apb";
0290 #dma-cells = <1>;
0291 xlnx,bus-width = <128>;
0292 iommus = <&smmu 0x14ea>;
0293 power-domains = <&zynqmp_firmware PD_GDMA>;
0294 };
0295
0296 fpd_dma_chan4: dma-controller@fd530000 {
0297 status = "disabled";
0298 compatible = "xlnx,zynqmp-dma-1.0";
0299 reg = <0x0 0xfd530000 0x0 0x1000>;
0300 interrupt-parent = <&gic>;
0301 interrupts = <0 127 4>;
0302 clock-names = "clk_main", "clk_apb";
0303 #dma-cells = <1>;
0304 xlnx,bus-width = <128>;
0305 iommus = <&smmu 0x14eb>;
0306 power-domains = <&zynqmp_firmware PD_GDMA>;
0307 };
0308
0309 fpd_dma_chan5: dma-controller@fd540000 {
0310 status = "disabled";
0311 compatible = "xlnx,zynqmp-dma-1.0";
0312 reg = <0x0 0xfd540000 0x0 0x1000>;
0313 interrupt-parent = <&gic>;
0314 interrupts = <0 128 4>;
0315 clock-names = "clk_main", "clk_apb";
0316 #dma-cells = <1>;
0317 xlnx,bus-width = <128>;
0318 iommus = <&smmu 0x14ec>;
0319 power-domains = <&zynqmp_firmware PD_GDMA>;
0320 };
0321
0322 fpd_dma_chan6: dma-controller@fd550000 {
0323 status = "disabled";
0324 compatible = "xlnx,zynqmp-dma-1.0";
0325 reg = <0x0 0xfd550000 0x0 0x1000>;
0326 interrupt-parent = <&gic>;
0327 interrupts = <0 129 4>;
0328 clock-names = "clk_main", "clk_apb";
0329 #dma-cells = <1>;
0330 xlnx,bus-width = <128>;
0331 iommus = <&smmu 0x14ed>;
0332 power-domains = <&zynqmp_firmware PD_GDMA>;
0333 };
0334
0335 fpd_dma_chan7: dma-controller@fd560000 {
0336 status = "disabled";
0337 compatible = "xlnx,zynqmp-dma-1.0";
0338 reg = <0x0 0xfd560000 0x0 0x1000>;
0339 interrupt-parent = <&gic>;
0340 interrupts = <0 130 4>;
0341 clock-names = "clk_main", "clk_apb";
0342 #dma-cells = <1>;
0343 xlnx,bus-width = <128>;
0344 iommus = <&smmu 0x14ee>;
0345 power-domains = <&zynqmp_firmware PD_GDMA>;
0346 };
0347
0348 fpd_dma_chan8: dma-controller@fd570000 {
0349 status = "disabled";
0350 compatible = "xlnx,zynqmp-dma-1.0";
0351 reg = <0x0 0xfd570000 0x0 0x1000>;
0352 interrupt-parent = <&gic>;
0353 interrupts = <0 131 4>;
0354 clock-names = "clk_main", "clk_apb";
0355 #dma-cells = <1>;
0356 xlnx,bus-width = <128>;
0357 iommus = <&smmu 0x14ef>;
0358 power-domains = <&zynqmp_firmware PD_GDMA>;
0359 };
0360
0361 gic: interrupt-controller@f9010000 {
0362 compatible = "arm,gic-400";
0363 #address-cells = <0>;
0364 #interrupt-cells = <3>;
0365 reg = <0x0 0xf9010000 0x0 0x10000>,
0366 <0x0 0xf9020000 0x0 0x20000>,
0367 <0x0 0xf9040000 0x0 0x20000>,
0368 <0x0 0xf9060000 0x0 0x20000>;
0369 interrupt-controller;
0370 interrupt-parent = <&gic>;
0371 interrupts = <1 9 0xf04>;
0372 };
0373
0374 /* LPDDMA default allows only secured access. inorder to enable
0375 * These dma channels, Users should ensure that these dma
0376 * Channels are allowed for non secure access.
0377 */
0378 lpd_dma_chan1: dma-controller@ffa80000 {
0379 status = "disabled";
0380 compatible = "xlnx,zynqmp-dma-1.0";
0381 reg = <0x0 0xffa80000 0x0 0x1000>;
0382 interrupt-parent = <&gic>;
0383 interrupts = <0 77 4>;
0384 clock-names = "clk_main", "clk_apb";
0385 #dma-cells = <1>;
0386 xlnx,bus-width = <64>;
0387 iommus = <&smmu 0x868>;
0388 power-domains = <&zynqmp_firmware PD_ADMA>;
0389 };
0390
0391 lpd_dma_chan2: dma-controller@ffa90000 {
0392 status = "disabled";
0393 compatible = "xlnx,zynqmp-dma-1.0";
0394 reg = <0x0 0xffa90000 0x0 0x1000>;
0395 interrupt-parent = <&gic>;
0396 interrupts = <0 78 4>;
0397 clock-names = "clk_main", "clk_apb";
0398 #dma-cells = <1>;
0399 xlnx,bus-width = <64>;
0400 iommus = <&smmu 0x869>;
0401 power-domains = <&zynqmp_firmware PD_ADMA>;
0402 };
0403
0404 lpd_dma_chan3: dma-controller@ffaa0000 {
0405 status = "disabled";
0406 compatible = "xlnx,zynqmp-dma-1.0";
0407 reg = <0x0 0xffaa0000 0x0 0x1000>;
0408 interrupt-parent = <&gic>;
0409 interrupts = <0 79 4>;
0410 clock-names = "clk_main", "clk_apb";
0411 #dma-cells = <1>;
0412 xlnx,bus-width = <64>;
0413 iommus = <&smmu 0x86a>;
0414 power-domains = <&zynqmp_firmware PD_ADMA>;
0415 };
0416
0417 lpd_dma_chan4: dma-controller@ffab0000 {
0418 status = "disabled";
0419 compatible = "xlnx,zynqmp-dma-1.0";
0420 reg = <0x0 0xffab0000 0x0 0x1000>;
0421 interrupt-parent = <&gic>;
0422 interrupts = <0 80 4>;
0423 clock-names = "clk_main", "clk_apb";
0424 #dma-cells = <1>;
0425 xlnx,bus-width = <64>;
0426 iommus = <&smmu 0x86b>;
0427 power-domains = <&zynqmp_firmware PD_ADMA>;
0428 };
0429
0430 lpd_dma_chan5: dma-controller@ffac0000 {
0431 status = "disabled";
0432 compatible = "xlnx,zynqmp-dma-1.0";
0433 reg = <0x0 0xffac0000 0x0 0x1000>;
0434 interrupt-parent = <&gic>;
0435 interrupts = <0 81 4>;
0436 clock-names = "clk_main", "clk_apb";
0437 #dma-cells = <1>;
0438 xlnx,bus-width = <64>;
0439 iommus = <&smmu 0x86c>;
0440 power-domains = <&zynqmp_firmware PD_ADMA>;
0441 };
0442
0443 lpd_dma_chan6: dma-controller@ffad0000 {
0444 status = "disabled";
0445 compatible = "xlnx,zynqmp-dma-1.0";
0446 reg = <0x0 0xffad0000 0x0 0x1000>;
0447 interrupt-parent = <&gic>;
0448 interrupts = <0 82 4>;
0449 clock-names = "clk_main", "clk_apb";
0450 #dma-cells = <1>;
0451 xlnx,bus-width = <64>;
0452 iommus = <&smmu 0x86d>;
0453 power-domains = <&zynqmp_firmware PD_ADMA>;
0454 };
0455
0456 lpd_dma_chan7: dma-controller@ffae0000 {
0457 status = "disabled";
0458 compatible = "xlnx,zynqmp-dma-1.0";
0459 reg = <0x0 0xffae0000 0x0 0x1000>;
0460 interrupt-parent = <&gic>;
0461 interrupts = <0 83 4>;
0462 clock-names = "clk_main", "clk_apb";
0463 #dma-cells = <1>;
0464 xlnx,bus-width = <64>;
0465 iommus = <&smmu 0x86e>;
0466 power-domains = <&zynqmp_firmware PD_ADMA>;
0467 };
0468
0469 lpd_dma_chan8: dma-controller@ffaf0000 {
0470 status = "disabled";
0471 compatible = "xlnx,zynqmp-dma-1.0";
0472 reg = <0x0 0xffaf0000 0x0 0x1000>;
0473 interrupt-parent = <&gic>;
0474 interrupts = <0 84 4>;
0475 clock-names = "clk_main", "clk_apb";
0476 #dma-cells = <1>;
0477 xlnx,bus-width = <64>;
0478 iommus = <&smmu 0x86f>;
0479 power-domains = <&zynqmp_firmware PD_ADMA>;
0480 };
0481
0482 mc: memory-controller@fd070000 {
0483 compatible = "xlnx,zynqmp-ddrc-2.40a";
0484 reg = <0x0 0xfd070000 0x0 0x30000>;
0485 interrupt-parent = <&gic>;
0486 interrupts = <0 112 4>;
0487 };
0488
0489 nand0: nand-controller@ff100000 {
0490 compatible = "xlnx,zynqmp-nand-controller", "arasan,nfc-v3p10";
0491 status = "disabled";
0492 reg = <0x0 0xff100000 0x0 0x1000>;
0493 clock-names = "controller", "bus";
0494 interrupt-parent = <&gic>;
0495 interrupts = <0 14 4>;
0496 #address-cells = <1>;
0497 #size-cells = <0>;
0498 iommus = <&smmu 0x872>;
0499 power-domains = <&zynqmp_firmware PD_NAND>;
0500 };
0501
0502 gem0: ethernet@ff0b0000 {
0503 compatible = "cdns,zynqmp-gem", "cdns,gem";
0504 status = "disabled";
0505 interrupt-parent = <&gic>;
0506 interrupts = <0 57 4>, <0 57 4>;
0507 reg = <0x0 0xff0b0000 0x0 0x1000>;
0508 clock-names = "pclk", "hclk", "tx_clk";
0509 #address-cells = <1>;
0510 #size-cells = <0>;
0511 iommus = <&smmu 0x874>;
0512 power-domains = <&zynqmp_firmware PD_ETH_0>;
0513 resets = <&zynqmp_reset ZYNQMP_RESET_GEM0>;
0514 reset-names = "gem0_rst";
0515 };
0516
0517 gem1: ethernet@ff0c0000 {
0518 compatible = "cdns,zynqmp-gem", "cdns,gem";
0519 status = "disabled";
0520 interrupt-parent = <&gic>;
0521 interrupts = <0 59 4>, <0 59 4>;
0522 reg = <0x0 0xff0c0000 0x0 0x1000>;
0523 clock-names = "pclk", "hclk", "tx_clk";
0524 #address-cells = <1>;
0525 #size-cells = <0>;
0526 iommus = <&smmu 0x875>;
0527 power-domains = <&zynqmp_firmware PD_ETH_1>;
0528 resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>;
0529 reset-names = "gem1_rst";
0530 };
0531
0532 gem2: ethernet@ff0d0000 {
0533 compatible = "cdns,zynqmp-gem", "cdns,gem";
0534 status = "disabled";
0535 interrupt-parent = <&gic>;
0536 interrupts = <0 61 4>, <0 61 4>;
0537 reg = <0x0 0xff0d0000 0x0 0x1000>;
0538 clock-names = "pclk", "hclk", "tx_clk";
0539 #address-cells = <1>;
0540 #size-cells = <0>;
0541 iommus = <&smmu 0x876>;
0542 power-domains = <&zynqmp_firmware PD_ETH_2>;
0543 resets = <&zynqmp_reset ZYNQMP_RESET_GEM2>;
0544 reset-names = "gem2_rst";
0545 };
0546
0547 gem3: ethernet@ff0e0000 {
0548 compatible = "cdns,zynqmp-gem", "cdns,gem";
0549 status = "disabled";
0550 interrupt-parent = <&gic>;
0551 interrupts = <0 63 4>, <0 63 4>;
0552 reg = <0x0 0xff0e0000 0x0 0x1000>;
0553 clock-names = "pclk", "hclk", "tx_clk";
0554 #address-cells = <1>;
0555 #size-cells = <0>;
0556 iommus = <&smmu 0x877>;
0557 power-domains = <&zynqmp_firmware PD_ETH_3>;
0558 resets = <&zynqmp_reset ZYNQMP_RESET_GEM3>;
0559 reset-names = "gem3_rst";
0560 };
0561
0562 gpio: gpio@ff0a0000 {
0563 compatible = "xlnx,zynqmp-gpio-1.0";
0564 status = "disabled";
0565 #address-cells = <0>;
0566 #gpio-cells = <0x2>;
0567 gpio-controller;
0568 interrupt-parent = <&gic>;
0569 interrupts = <0 16 4>;
0570 interrupt-controller;
0571 #interrupt-cells = <2>;
0572 reg = <0x0 0xff0a0000 0x0 0x1000>;
0573 power-domains = <&zynqmp_firmware PD_GPIO>;
0574 };
0575
0576 i2c0: i2c@ff020000 {
0577 compatible = "cdns,i2c-r1p14";
0578 status = "disabled";
0579 interrupt-parent = <&gic>;
0580 interrupts = <0 17 4>;
0581 reg = <0x0 0xff020000 0x0 0x1000>;
0582 #address-cells = <1>;
0583 #size-cells = <0>;
0584 power-domains = <&zynqmp_firmware PD_I2C_0>;
0585 };
0586
0587 i2c1: i2c@ff030000 {
0588 compatible = "cdns,i2c-r1p14";
0589 status = "disabled";
0590 interrupt-parent = <&gic>;
0591 interrupts = <0 18 4>;
0592 reg = <0x0 0xff030000 0x0 0x1000>;
0593 #address-cells = <1>;
0594 #size-cells = <0>;
0595 power-domains = <&zynqmp_firmware PD_I2C_1>;
0596 };
0597
0598 pcie: pcie@fd0e0000 {
0599 compatible = "xlnx,nwl-pcie-2.11";
0600 status = "disabled";
0601 #address-cells = <3>;
0602 #size-cells = <2>;
0603 #interrupt-cells = <1>;
0604 msi-controller;
0605 device_type = "pci";
0606 interrupt-parent = <&gic>;
0607 interrupts = <0 118 4>,
0608 <0 117 4>,
0609 <0 116 4>,
0610 <0 115 4>, /* MSI_1 [63...32] */
0611 <0 114 4>; /* MSI_0 [31...0] */
0612 interrupt-names = "misc", "dummy", "intx",
0613 "msi1", "msi0";
0614 msi-parent = <&pcie>;
0615 reg = <0x0 0xfd0e0000 0x0 0x1000>,
0616 <0x0 0xfd480000 0x0 0x1000>,
0617 <0x80 0x00000000 0x0 0x1000000>;
0618 reg-names = "breg", "pcireg", "cfg";
0619 ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000>,/* non-prefetchable memory */
0620 <0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
0621 bus-range = <0x00 0xff>;
0622 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
0623 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
0624 <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
0625 <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
0626 <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
0627 iommus = <&smmu 0x4d0>;
0628 power-domains = <&zynqmp_firmware PD_PCIE>;
0629 pcie_intc: legacy-interrupt-controller {
0630 interrupt-controller;
0631 #address-cells = <0>;
0632 #interrupt-cells = <1>;
0633 };
0634 };
0635
0636 qspi: spi@ff0f0000 {
0637 compatible = "xlnx,zynqmp-qspi-1.0";
0638 status = "disabled";
0639 clock-names = "ref_clk", "pclk";
0640 interrupts = <0 15 4>;
0641 interrupt-parent = <&gic>;
0642 num-cs = <1>;
0643 reg = <0x0 0xff0f0000 0x0 0x1000>,
0644 <0x0 0xc0000000 0x0 0x8000000>;
0645 #address-cells = <1>;
0646 #size-cells = <0>;
0647 iommus = <&smmu 0x873>;
0648 power-domains = <&zynqmp_firmware PD_QSPI>;
0649 };
0650
0651 psgtr: phy@fd400000 {
0652 compatible = "xlnx,zynqmp-psgtr-v1.1";
0653 status = "disabled";
0654 reg = <0x0 0xfd400000 0x0 0x40000>,
0655 <0x0 0xfd3d0000 0x0 0x1000>;
0656 reg-names = "serdes", "siou";
0657 #phy-cells = <4>;
0658 };
0659
0660 rtc: rtc@ffa60000 {
0661 compatible = "xlnx,zynqmp-rtc";
0662 status = "disabled";
0663 reg = <0x0 0xffa60000 0x0 0x100>;
0664 interrupt-parent = <&gic>;
0665 interrupts = <0 26 4>, <0 27 4>;
0666 interrupt-names = "alarm", "sec";
0667 calibration = <0x7FFF>;
0668 };
0669
0670 sata: ahci@fd0c0000 {
0671 compatible = "ceva,ahci-1v84";
0672 status = "disabled";
0673 reg = <0x0 0xfd0c0000 0x0 0x2000>;
0674 interrupt-parent = <&gic>;
0675 interrupts = <0 133 4>;
0676 power-domains = <&zynqmp_firmware PD_SATA>;
0677 resets = <&zynqmp_reset ZYNQMP_RESET_SATA>;
0678 iommus = <&smmu 0x4c0>, <&smmu 0x4c1>,
0679 <&smmu 0x4c2>, <&smmu 0x4c3>;
0680 };
0681
0682 sdhci0: mmc@ff160000 {
0683 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
0684 status = "disabled";
0685 interrupt-parent = <&gic>;
0686 interrupts = <0 48 4>;
0687 reg = <0x0 0xff160000 0x0 0x1000>;
0688 clock-names = "clk_xin", "clk_ahb";
0689 iommus = <&smmu 0x870>;
0690 #clock-cells = <1>;
0691 clock-output-names = "clk_out_sd0", "clk_in_sd0";
0692 power-domains = <&zynqmp_firmware PD_SD_0>;
0693 };
0694
0695 sdhci1: mmc@ff170000 {
0696 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
0697 status = "disabled";
0698 interrupt-parent = <&gic>;
0699 interrupts = <0 49 4>;
0700 reg = <0x0 0xff170000 0x0 0x1000>;
0701 clock-names = "clk_xin", "clk_ahb";
0702 iommus = <&smmu 0x871>;
0703 #clock-cells = <1>;
0704 clock-output-names = "clk_out_sd1", "clk_in_sd1";
0705 power-domains = <&zynqmp_firmware PD_SD_1>;
0706 };
0707
0708 smmu: iommu@fd800000 {
0709 compatible = "arm,mmu-500";
0710 reg = <0x0 0xfd800000 0x0 0x20000>;
0711 #iommu-cells = <1>;
0712 status = "disabled";
0713 #global-interrupts = <1>;
0714 interrupt-parent = <&gic>;
0715 interrupts = <0 155 4>,
0716 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
0717 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
0718 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
0719 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;
0720 };
0721
0722 spi0: spi@ff040000 {
0723 compatible = "cdns,spi-r1p6";
0724 status = "disabled";
0725 interrupt-parent = <&gic>;
0726 interrupts = <0 19 4>;
0727 reg = <0x0 0xff040000 0x0 0x1000>;
0728 clock-names = "ref_clk", "pclk";
0729 #address-cells = <1>;
0730 #size-cells = <0>;
0731 power-domains = <&zynqmp_firmware PD_SPI_0>;
0732 };
0733
0734 spi1: spi@ff050000 {
0735 compatible = "cdns,spi-r1p6";
0736 status = "disabled";
0737 interrupt-parent = <&gic>;
0738 interrupts = <0 20 4>;
0739 reg = <0x0 0xff050000 0x0 0x1000>;
0740 clock-names = "ref_clk", "pclk";
0741 #address-cells = <1>;
0742 #size-cells = <0>;
0743 power-domains = <&zynqmp_firmware PD_SPI_1>;
0744 };
0745
0746 ttc0: timer@ff110000 {
0747 compatible = "cdns,ttc";
0748 status = "disabled";
0749 interrupt-parent = <&gic>;
0750 interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
0751 reg = <0x0 0xff110000 0x0 0x1000>;
0752 timer-width = <32>;
0753 power-domains = <&zynqmp_firmware PD_TTC_0>;
0754 };
0755
0756 ttc1: timer@ff120000 {
0757 compatible = "cdns,ttc";
0758 status = "disabled";
0759 interrupt-parent = <&gic>;
0760 interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
0761 reg = <0x0 0xff120000 0x0 0x1000>;
0762 timer-width = <32>;
0763 power-domains = <&zynqmp_firmware PD_TTC_1>;
0764 };
0765
0766 ttc2: timer@ff130000 {
0767 compatible = "cdns,ttc";
0768 status = "disabled";
0769 interrupt-parent = <&gic>;
0770 interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
0771 reg = <0x0 0xff130000 0x0 0x1000>;
0772 timer-width = <32>;
0773 power-domains = <&zynqmp_firmware PD_TTC_2>;
0774 };
0775
0776 ttc3: timer@ff140000 {
0777 compatible = "cdns,ttc";
0778 status = "disabled";
0779 interrupt-parent = <&gic>;
0780 interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
0781 reg = <0x0 0xff140000 0x0 0x1000>;
0782 timer-width = <32>;
0783 power-domains = <&zynqmp_firmware PD_TTC_3>;
0784 };
0785
0786 uart0: serial@ff000000 {
0787 compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
0788 status = "disabled";
0789 interrupt-parent = <&gic>;
0790 interrupts = <0 21 4>;
0791 reg = <0x0 0xff000000 0x0 0x1000>;
0792 clock-names = "uart_clk", "pclk";
0793 power-domains = <&zynqmp_firmware PD_UART_0>;
0794 };
0795
0796 uart1: serial@ff010000 {
0797 compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
0798 status = "disabled";
0799 interrupt-parent = <&gic>;
0800 interrupts = <0 22 4>;
0801 reg = <0x0 0xff010000 0x0 0x1000>;
0802 clock-names = "uart_clk", "pclk";
0803 power-domains = <&zynqmp_firmware PD_UART_1>;
0804 };
0805
0806 usb0: usb@ff9d0000 {
0807 #address-cells = <2>;
0808 #size-cells = <2>;
0809 status = "disabled";
0810 compatible = "xlnx,zynqmp-dwc3";
0811 reg = <0x0 0xff9d0000 0x0 0x100>;
0812 power-domains = <&zynqmp_firmware PD_USB_0>;
0813 resets = <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>,
0814 <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>,
0815 <&zynqmp_reset ZYNQMP_RESET_USB0_APB>;
0816 reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
0817 ranges;
0818
0819 dwc3_0: usb@fe200000 {
0820 compatible = "snps,dwc3";
0821 reg = <0x0 0xfe200000 0x0 0x40000>;
0822 interrupt-parent = <&gic>;
0823 interrupt-names = "dwc_usb3", "otg";
0824 interrupts = <0 65 4>, <0 69 4>;
0825 clock-names = "bus_early", "ref";
0826 iommus = <&smmu 0x860>;
0827 snps,quirk-frame-length-adjustment = <0x20>;
0828 /* dma-coherent; */
0829 };
0830 };
0831
0832 usb1: usb@ff9e0000 {
0833 #address-cells = <2>;
0834 #size-cells = <2>;
0835 status = "disabled";
0836 compatible = "xlnx,zynqmp-dwc3";
0837 reg = <0x0 0xff9e0000 0x0 0x100>;
0838 power-domains = <&zynqmp_firmware PD_USB_1>;
0839 resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>,
0840 <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>,
0841 <&zynqmp_reset ZYNQMP_RESET_USB1_APB>;
0842 reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
0843 ranges;
0844
0845 dwc3_1: usb@fe300000 {
0846 compatible = "snps,dwc3";
0847 reg = <0x0 0xfe300000 0x0 0x40000>;
0848 interrupt-parent = <&gic>;
0849 interrupt-names = "dwc_usb3", "otg";
0850 interrupts = <0 70 4>, <0 74 4>;
0851 clock-names = "bus_early", "ref";
0852 iommus = <&smmu 0x861>;
0853 snps,quirk-frame-length-adjustment = <0x20>;
0854 /* dma-coherent; */
0855 };
0856 };
0857
0858 watchdog0: watchdog@fd4d0000 {
0859 compatible = "cdns,wdt-r1p2";
0860 status = "disabled";
0861 interrupt-parent = <&gic>;
0862 interrupts = <0 113 1>;
0863 reg = <0x0 0xfd4d0000 0x0 0x1000>;
0864 timeout-sec = <60>;
0865 reset-on-timeout;
0866 };
0867
0868 lpd_watchdog: watchdog@ff150000 {
0869 compatible = "cdns,wdt-r1p2";
0870 status = "disabled";
0871 interrupt-parent = <&gic>;
0872 interrupts = <0 52 1>;
0873 reg = <0x0 0xff150000 0x0 0x1000>;
0874 timeout-sec = <10>;
0875 };
0876
0877 xilinx_ams: ams@ffa50000 {
0878 compatible = "xlnx,zynqmp-ams";
0879 status = "disabled";
0880 interrupt-parent = <&gic>;
0881 interrupts = <0 56 4>;
0882 reg = <0x0 0xffa50000 0x0 0x800>;
0883 #address-cells = <1>;
0884 #size-cells = <1>;
0885 #io-channel-cells = <1>;
0886 ranges = <0 0 0xffa50800 0x800>;
0887
0888 ams_ps: ams_ps@0 {
0889 compatible = "xlnx,zynqmp-ams-ps";
0890 status = "disabled";
0891 reg = <0x0 0x400>;
0892 };
0893
0894 ams_pl: ams_pl@400 {
0895 compatible = "xlnx,zynqmp-ams-pl";
0896 status = "disabled";
0897 reg = <0x400 0x400>;
0898 #address-cells = <1>;
0899 #size-cells = <0>;
0900 };
0901 };
0902
0903 zynqmp_dpdma: dma-controller@fd4c0000 {
0904 compatible = "xlnx,zynqmp-dpdma";
0905 status = "disabled";
0906 reg = <0x0 0xfd4c0000 0x0 0x1000>;
0907 interrupts = <0 122 4>;
0908 interrupt-parent = <&gic>;
0909 clock-names = "axi_clk";
0910 power-domains = <&zynqmp_firmware PD_DP>;
0911 #dma-cells = <1>;
0912 };
0913
0914 zynqmp_dpsub: display@fd4a0000 {
0915 compatible = "xlnx,zynqmp-dpsub-1.7";
0916 status = "disabled";
0917 reg = <0x0 0xfd4a0000 0x0 0x1000>,
0918 <0x0 0xfd4aa000 0x0 0x1000>,
0919 <0x0 0xfd4ab000 0x0 0x1000>,
0920 <0x0 0xfd4ac000 0x0 0x1000>;
0921 reg-names = "dp", "blend", "av_buf", "aud";
0922 interrupts = <0 119 4>;
0923 interrupt-parent = <&gic>;
0924 clock-names = "dp_apb_clk", "dp_aud_clk",
0925 "dp_vtc_pixel_clk_in";
0926 power-domains = <&zynqmp_firmware PD_DP>;
0927 resets = <&zynqmp_reset ZYNQMP_RESET_DP>;
0928 dma-names = "vid0", "vid1", "vid2", "gfx0";
0929 dmas = <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO0>,
0930 <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>,
0931 <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>,
0932 <&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>;
0933 };
0934 };
0935 };
