0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003 * dts file for Xilinx ZynqMP ZCU111
0004 *
0005 * (C) Copyright 2017 - 2021, Xilinx, Inc.
0006 *
0007 * Michal Simek <michal.simek@xilinx.com>
0008 */
0009
0010 /dts-v1/;
0011
0012 #include "zynqmp.dtsi"
0013 #include "zynqmp-clk-ccf.dtsi"
0014 #include <dt-bindings/input/input.h>
0015 #include <dt-bindings/gpio/gpio.h>
0016 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
0017 #include <dt-bindings/phy/phy.h>
0018
0019 / {
0020 model = "ZynqMP ZCU111 RevA";
0021 compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp";
0022
0023 aliases {
0024 ethernet0 = &gem3;
0025 i2c0 = &i2c0;
0026 i2c1 = &i2c1;
0027 mmc0 = &sdhci1;
0028 nvmem0 = &eeprom;
0029 rtc0 = &rtc;
0030 serial0 = &uart0;
0031 serial1 = &dcc;
0032 spi0 = &qspi;
0033 usb0 = &usb0;
0034 };
0035
0036 chosen {
0037 bootargs = "earlycon";
0038 stdout-path = "serial0:115200n8";
0039 };
0040
0041 memory@0 {
0042 device_type = "memory";
0043 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
0044 /* Another 4GB connected to PL */
0045 };
0046
0047 gpio-keys {
0048 compatible = "gpio-keys";
0049 autorepeat;
0050 switch-19 {
0051 label = "sw19";
0052 gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
0053 linux,code = <KEY_DOWN>;
0054 wakeup-source;
0055 autorepeat;
0056 };
0057 };
0058
0059 leds {
0060 compatible = "gpio-leds";
0061 heartbeat-led {
0062 label = "heartbeat";
0063 gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
0064 linux,default-trigger = "heartbeat";
0065 };
0066 };
0067
0068 ina226-u67 {
0069 compatible = "iio-hwmon";
0070 io-channels = <&u67 0>, <&u67 1>, <&u67 2>, <&u67 3>;
0071 };
0072 ina226-u59 {
0073 compatible = "iio-hwmon";
0074 io-channels = <&u59 0>, <&u59 1>, <&u59 2>, <&u59 3>;
0075 };
0076 ina226-u61 {
0077 compatible = "iio-hwmon";
0078 io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>;
0079 };
0080 ina226-u60 {
0081 compatible = "iio-hwmon";
0082 io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>;
0083 };
0084 ina226-u64 {
0085 compatible = "iio-hwmon";
0086 io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>;
0087 };
0088 ina226-u69 {
0089 compatible = "iio-hwmon";
0090 io-channels = <&u69 0>, <&u69 1>, <&u69 2>, <&u69 3>;
0091 };
0092 ina226-u66 {
0093 compatible = "iio-hwmon";
0094 io-channels = <&u66 0>, <&u66 1>, <&u66 2>, <&u66 3>;
0095 };
0096 ina226-u65 {
0097 compatible = "iio-hwmon";
0098 io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
0099 };
0100 ina226-u63 {
0101 compatible = "iio-hwmon";
0102 io-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>;
0103 };
0104 ina226-u3 {
0105 compatible = "iio-hwmon";
0106 io-channels = <&u3 0>, <&u3 1>, <&u3 2>, <&u3 3>;
0107 };
0108 ina226-u71 {
0109 compatible = "iio-hwmon";
0110 io-channels = <&u71 0>, <&u71 1>, <&u71 2>, <&u71 3>;
0111 };
0112 ina226-u77 {
0113 compatible = "iio-hwmon";
0114 io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
0115 };
0116 ina226-u73 {
0117 compatible = "iio-hwmon";
0118 io-channels = <&u73 0>, <&u73 1>, <&u73 2>, <&u73 3>;
0119 };
0120 ina226-u79 {
0121 compatible = "iio-hwmon";
0122 io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
0123 };
0124
0125 /* 48MHz reference crystal */
0126 ref48: ref48M {
0127 compatible = "fixed-clock";
0128 #clock-cells = <0>;
0129 clock-frequency = <48000000>;
0130 };
0131 };
0132
0133 &dcc {
0134 status = "okay";
0135 };
0136
0137 &fpd_dma_chan1 {
0138 status = "okay";
0139 };
0140
0141 &fpd_dma_chan2 {
0142 status = "okay";
0143 };
0144
0145 &fpd_dma_chan3 {
0146 status = "okay";
0147 };
0148
0149 &fpd_dma_chan4 {
0150 status = "okay";
0151 };
0152
0153 &fpd_dma_chan5 {
0154 status = "okay";
0155 };
0156
0157 &fpd_dma_chan6 {
0158 status = "okay";
0159 };
0160
0161 &fpd_dma_chan7 {
0162 status = "okay";
0163 };
0164
0165 &fpd_dma_chan8 {
0166 status = "okay";
0167 };
0168
0169 &gem3 {
0170 status = "okay";
0171 phy-handle = <&phy0>;
0172 phy-mode = "rgmii-id";
0173 pinctrl-names = "default";
0174 pinctrl-0 = <&pinctrl_gem3_default>;
0175 phy0: ethernet-phy@c {
0176 reg = <0xc>;
0177 ti,rx-internal-delay = <0x8>;
0178 ti,tx-internal-delay = <0xa>;
0179 ti,fifo-depth = <0x1>;
0180 ti,dp83867-rxctrl-strap-quirk;
0181 };
0182 };
0183
0184 &gpio {
0185 status = "okay";
0186 pinctrl-names = "default";
0187 pinctrl-0 = <&pinctrl_gpio_default>;
0188 };
0189
0190 &i2c0 {
0191 status = "okay";
0192 clock-frequency = <400000>;
0193 pinctrl-names = "default", "gpio";
0194 pinctrl-0 = <&pinctrl_i2c0_default>;
0195 pinctrl-1 = <&pinctrl_i2c0_gpio>;
0196 scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
0197 sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
0198
0199 tca6416_u22: gpio@20 {
0200 compatible = "ti,tca6416";
0201 reg = <0x20>;
0202 gpio-controller; /* interrupt not connected */
0203 #gpio-cells = <2>;
0204 /*
0205 * IRQ not connected
0206 * Lines:
0207 * 0 - MAX6643_OT_B
0208 * 1 - MAX6643_FANFAIL_B
0209 * 2 - MIO26_PMU_INPUT_LS
0210 * 4 - SFP_SI5382_INT_ALM
0211 * 5 - IIC_MUX_RESET_B
0212 * 6 - GEM3_EXP_RESET_B
0213 * 10 - FMCP_HSPC_PRSNT_M2C_B
0214 * 11 - CLK_SPI_MUX_SEL0
0215 * 12 - CLK_SPI_MUX_SEL1
0216 * 16 - IRPS5401_ALERT_B
0217 * 17 - INA226_PMBUS_ALERT
0218 * 3, 7, 13-15 - not connected
0219 */
0220 };
0221
0222 i2c-mux@75 { /* u23 */
0223 compatible = "nxp,pca9544";
0224 #address-cells = <1>;
0225 #size-cells = <0>;
0226 reg = <0x75>;
0227 i2c@0 {
0228 #address-cells = <1>;
0229 #size-cells = <0>;
0230 reg = <0>;
0231 /* PS_PMBUS */
0232 /* PMBUS_ALERT done via pca9544 */
0233 u67: ina226@40 { /* u67 */
0234 compatible = "ti,ina226";
0235 #io-channel-cells = <1>;
0236 label = "ina226-u67";
0237 reg = <0x40>;
0238 shunt-resistor = <2000>;
0239 };
0240 u59: ina226@41 { /* u59 */
0241 compatible = "ti,ina226";
0242 #io-channel-cells = <1>;
0243 label = "ina226-u59";
0244 reg = <0x41>;
0245 shunt-resistor = <5000>;
0246 };
0247 u61: ina226@42 { /* u61 */
0248 compatible = "ti,ina226";
0249 #io-channel-cells = <1>;
0250 label = "ina226-u61";
0251 reg = <0x42>;
0252 shunt-resistor = <5000>;
0253 };
0254 u60: ina226@43 { /* u60 */
0255 compatible = "ti,ina226";
0256 #io-channel-cells = <1>;
0257 label = "ina226-u60";
0258 reg = <0x43>;
0259 shunt-resistor = <5000>;
0260 };
0261 u64: ina226@45 { /* u64 */
0262 compatible = "ti,ina226";
0263 #io-channel-cells = <1>;
0264 label = "ina226-u64";
0265 reg = <0x45>;
0266 shunt-resistor = <5000>;
0267 };
0268 u69: ina226@46 { /* u69 */
0269 compatible = "ti,ina226";
0270 #io-channel-cells = <1>;
0271 label = "ina226-u69";
0272 reg = <0x46>;
0273 shunt-resistor = <2000>;
0274 };
0275 u66: ina226@47 { /* u66 */
0276 compatible = "ti,ina226";
0277 #io-channel-cells = <1>;
0278 label = "ina226-u66";
0279 reg = <0x47>;
0280 shunt-resistor = <5000>;
0281 };
0282 u65: ina226@48 { /* u65 */
0283 compatible = "ti,ina226";
0284 #io-channel-cells = <1>;
0285 label = "ina226-u65";
0286 reg = <0x48>;
0287 shunt-resistor = <5000>;
0288 };
0289 u63: ina226@49 { /* u63 */
0290 compatible = "ti,ina226";
0291 #io-channel-cells = <1>;
0292 label = "ina226-u63";
0293 reg = <0x49>;
0294 shunt-resistor = <5000>;
0295 };
0296 u3: ina226@4a { /* u3 */
0297 compatible = "ti,ina226";
0298 #io-channel-cells = <1>;
0299 label = "ina226-u3";
0300 reg = <0x4a>;
0301 shunt-resistor = <5000>;
0302 };
0303 u71: ina226@4b { /* u71 */
0304 compatible = "ti,ina226";
0305 #io-channel-cells = <1>;
0306 label = "ina226-u71";
0307 reg = <0x4b>;
0308 shunt-resistor = <5000>;
0309 };
0310 u77: ina226@4c { /* u77 */
0311 compatible = "ti,ina226";
0312 #io-channel-cells = <1>;
0313 label = "ina226-u77";
0314 reg = <0x4c>;
0315 shunt-resistor = <5000>;
0316 };
0317 u73: ina226@4d { /* u73 */
0318 compatible = "ti,ina226";
0319 #io-channel-cells = <1>;
0320 label = "ina226-u73";
0321 reg = <0x4d>;
0322 shunt-resistor = <5000>;
0323 };
0324 u79: ina226@4e { /* u79 */
0325 compatible = "ti,ina226";
0326 #io-channel-cells = <1>;
0327 label = "ina226-u79";
0328 reg = <0x4e>;
0329 shunt-resistor = <5000>;
0330 };
0331 };
0332 i2c@1 {
0333 #address-cells = <1>;
0334 #size-cells = <0>;
0335 reg = <1>;
0336 /* NC */
0337 };
0338 i2c@2 {
0339 #address-cells = <1>;
0340 #size-cells = <0>;
0341 reg = <2>;
0342 irps5401_43: irps5401@43 { /* IRPS5401 - u53 check these */
0343 compatible = "infineon,irps5401";
0344 reg = <0x43>;
0345 };
0346 irps5401_44: irps5401@44 { /* IRPS5401 - u55 */
0347 compatible = "infineon,irps5401";
0348 reg = <0x44>;
0349 };
0350 irps5401_45: irps5401@45 { /* IRPS5401 - u57 */
0351 compatible = "infineon,irps5401";
0352 reg = <0x45>;
0353 };
0354 /* u68 IR38064 +0 */
0355 /* u70 IR38060 +1 */
0356 /* u74 IR38060 +2 */
0357 /* u75 IR38060 +6 */
0358 /* J19 header too */
0359
0360 };
0361 i2c@3 {
0362 #address-cells = <1>;
0363 #size-cells = <0>;
0364 reg = <3>;
0365 /* SYSMON */
0366 };
0367 };
0368 };
0369
0370 &i2c1 {
0371 status = "okay";
0372 clock-frequency = <400000>;
0373 pinctrl-names = "default", "gpio";
0374 pinctrl-0 = <&pinctrl_i2c1_default>;
0375 pinctrl-1 = <&pinctrl_i2c1_gpio>;
0376 scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
0377 sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
0378
0379 i2c-mux@74 { /* u26 */
0380 compatible = "nxp,pca9548";
0381 #address-cells = <1>;
0382 #size-cells = <0>;
0383 reg = <0x74>;
0384 i2c@0 {
0385 #address-cells = <1>;
0386 #size-cells = <0>;
0387 reg = <0>;
0388 /*
0389 * IIC_EEPROM 1kB memory which uses 256B blocks
0390 * where every block has different address.
0391 * 0 - 256B address 0x54
0392 * 256B - 512B address 0x55
0393 * 512B - 768B address 0x56
0394 * 768B - 1024B address 0x57
0395 */
0396 eeprom: eeprom@54 { /* u88 */
0397 compatible = "atmel,24c08";
0398 reg = <0x54>;
0399 };
0400 };
0401 i2c@1 {
0402 #address-cells = <1>;
0403 #size-cells = <0>;
0404 reg = <1>;
0405 si5341: clock-generator@36 { /* SI5341 - u46 */
0406 compatible = "silabs,si5341";
0407 reg = <0x36>;
0408 #clock-cells = <2>;
0409 #address-cells = <1>;
0410 #size-cells = <0>;
0411 clocks = <&ref48>;
0412 clock-names = "xtal";
0413 clock-output-names = "si5341";
0414
0415 si5341_0: out@0 {
0416 /* refclk0 for PS-GT, used for DP */
0417 reg = <0>;
0418 always-on;
0419 };
0420 si5341_2: out@2 {
0421 /* refclk2 for PS-GT, used for USB3 */
0422 reg = <2>;
0423 always-on;
0424 };
0425 si5341_3: out@3 {
0426 /* refclk3 for PS-GT, used for SATA */
0427 reg = <3>;
0428 always-on;
0429 };
0430 si5341_5: out@5 {
0431 /* refclk5 PL CLK100 */
0432 reg = <5>;
0433 always-on;
0434 };
0435 si5341_6: out@6 {
0436 /* refclk6 PL CLK125 */
0437 reg = <6>;
0438 always-on;
0439 };
0440 si5341_9: out@9 {
0441 /* refclk9 used for PS_REF_CLK 33.3 MHz */
0442 reg = <9>;
0443 always-on;
0444 };
0445 };
0446 };
0447 i2c@2 {
0448 #address-cells = <1>;
0449 #size-cells = <0>;
0450 reg = <2>;
0451 si570_1: clock-generator@5d { /* USER SI570 - u47 */
0452 #clock-cells = <0>;
0453 compatible = "silabs,si570";
0454 reg = <0x5d>;
0455 temperature-stability = <50>;
0456 factory-fout = <300000000>;
0457 clock-frequency = <300000000>;
0458 clock-output-names = "si570_user";
0459 };
0460 };
0461 i2c@3 {
0462 #address-cells = <1>;
0463 #size-cells = <0>;
0464 reg = <3>;
0465 si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */
0466 #clock-cells = <0>;
0467 compatible = "silabs,si570";
0468 reg = <0x5d>;
0469 temperature-stability = <50>;
0470 factory-fout = <156250000>;
0471 clock-frequency = <156250000>;
0472 clock-output-names = "si570_mgt";
0473 };
0474 };
0475 i2c@4 {
0476 #address-cells = <1>;
0477 #size-cells = <0>;
0478 reg = <4>;
0479 /* SI5382 - u48 */
0480 };
0481 i2c@5 {
0482 #address-cells = <1>;
0483 #size-cells = <0>;
0484 reg = <5>;
0485 sc18is603@2f { /* sc18is602 - u93 */
0486 compatible = "nxp,sc18is603";
0487 reg = <0x2f>;
0488 /* 4 gpios for CS not handled by driver */
0489 /*
0490 * USB2ANY cable or
0491 * LMK04208 - u90 or
0492 * LMX2594 - u102 or
0493 * LMX2594 - u103 or
0494 * LMX2594 - u104
0495 */
0496 };
0497 };
0498 i2c@6 {
0499 #address-cells = <1>;
0500 #size-cells = <0>;
0501 reg = <6>;
0502 /* FMC connector */
0503 };
0504 /* 7 NC */
0505 };
0506
0507 i2c-mux@75 {
0508 compatible = "nxp,pca9548"; /* u27 */
0509 #address-cells = <1>;
0510 #size-cells = <0>;
0511 reg = <0x75>;
0512
0513 i2c@0 {
0514 #address-cells = <1>;
0515 #size-cells = <0>;
0516 reg = <0>;
0517 /* FMCP_HSPC_IIC */
0518 };
0519 i2c@1 {
0520 #address-cells = <1>;
0521 #size-cells = <0>;
0522 reg = <1>;
0523 /* NC */
0524 };
0525 i2c@2 {
0526 #address-cells = <1>;
0527 #size-cells = <0>;
0528 reg = <2>;
0529 /* SYSMON */
0530 };
0531 i2c@3 {
0532 #address-cells = <1>;
0533 #size-cells = <0>;
0534 reg = <3>;
0535 /* DDR4 SODIMM */
0536 };
0537 i2c@4 {
0538 #address-cells = <1>;
0539 #size-cells = <0>;
0540 reg = <4>;
0541 /* SFP3 */
0542 };
0543 i2c@5 {
0544 #address-cells = <1>;
0545 #size-cells = <0>;
0546 reg = <5>;
0547 /* SFP2 */
0548 };
0549 i2c@6 {
0550 #address-cells = <1>;
0551 #size-cells = <0>;
0552 reg = <6>;
0553 /* SFP1 */
0554 };
0555 i2c@7 {
0556 #address-cells = <1>;
0557 #size-cells = <0>;
0558 reg = <7>;
0559 /* SFP0 */
0560 };
0561 };
0562 };
0563
0564 &pinctrl0 {
0565 status = "okay";
0566 pinctrl_i2c0_default: i2c0-default {
0567 mux {
0568 groups = "i2c0_3_grp";
0569 function = "i2c0";
0570 };
0571
0572 conf {
0573 groups = "i2c0_3_grp";
0574 bias-pull-up;
0575 slew-rate = <SLEW_RATE_SLOW>;
0576 power-source = <IO_STANDARD_LVCMOS18>;
0577 };
0578 };
0579
0580 pinctrl_i2c0_gpio: i2c0-gpio {
0581 mux {
0582 groups = "gpio0_14_grp", "gpio0_15_grp";
0583 function = "gpio0";
0584 };
0585
0586 conf {
0587 groups = "gpio0_14_grp", "gpio0_15_grp";
0588 slew-rate = <SLEW_RATE_SLOW>;
0589 power-source = <IO_STANDARD_LVCMOS18>;
0590 };
0591 };
0592
0593 pinctrl_i2c1_default: i2c1-default {
0594 mux {
0595 groups = "i2c1_4_grp";
0596 function = "i2c1";
0597 };
0598
0599 conf {
0600 groups = "i2c1_4_grp";
0601 bias-pull-up;
0602 slew-rate = <SLEW_RATE_SLOW>;
0603 power-source = <IO_STANDARD_LVCMOS18>;
0604 };
0605 };
0606
0607 pinctrl_i2c1_gpio: i2c1-gpio {
0608 mux {
0609 groups = "gpio0_16_grp", "gpio0_17_grp";
0610 function = "gpio0";
0611 };
0612
0613 conf {
0614 groups = "gpio0_16_grp", "gpio0_17_grp";
0615 slew-rate = <SLEW_RATE_SLOW>;
0616 power-source = <IO_STANDARD_LVCMOS18>;
0617 };
0618 };
0619
0620 pinctrl_uart0_default: uart0-default {
0621 mux {
0622 groups = "uart0_4_grp";
0623 function = "uart0";
0624 };
0625
0626 conf {
0627 groups = "uart0_4_grp";
0628 slew-rate = <SLEW_RATE_SLOW>;
0629 power-source = <IO_STANDARD_LVCMOS18>;
0630 };
0631
0632 conf-rx {
0633 pins = "MIO18";
0634 bias-high-impedance;
0635 };
0636
0637 conf-tx {
0638 pins = "MIO19";
0639 bias-disable;
0640 };
0641 };
0642
0643 pinctrl_usb0_default: usb0-default {
0644 mux {
0645 groups = "usb0_0_grp";
0646 function = "usb0";
0647 };
0648
0649 conf {
0650 groups = "usb0_0_grp";
0651 slew-rate = <SLEW_RATE_SLOW>;
0652 power-source = <IO_STANDARD_LVCMOS18>;
0653 };
0654
0655 conf-rx {
0656 pins = "MIO52", "MIO53", "MIO55";
0657 bias-high-impedance;
0658 };
0659
0660 conf-tx {
0661 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
0662 "MIO60", "MIO61", "MIO62", "MIO63";
0663 bias-disable;
0664 };
0665 };
0666
0667 pinctrl_gem3_default: gem3-default {
0668 mux {
0669 function = "ethernet3";
0670 groups = "ethernet3_0_grp";
0671 };
0672
0673 conf {
0674 groups = "ethernet3_0_grp";
0675 slew-rate = <SLEW_RATE_SLOW>;
0676 power-source = <IO_STANDARD_LVCMOS18>;
0677 };
0678
0679 conf-rx {
0680 pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
0681 "MIO75";
0682 bias-high-impedance;
0683 low-power-disable;
0684 };
0685
0686 conf-tx {
0687 pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
0688 "MIO69";
0689 bias-disable;
0690 low-power-enable;
0691 };
0692
0693 mux-mdio {
0694 function = "mdio3";
0695 groups = "mdio3_0_grp";
0696 };
0697
0698 conf-mdio {
0699 groups = "mdio3_0_grp";
0700 slew-rate = <SLEW_RATE_SLOW>;
0701 power-source = <IO_STANDARD_LVCMOS18>;
0702 bias-disable;
0703 };
0704 };
0705
0706 pinctrl_sdhci1_default: sdhci1-default {
0707 mux {
0708 groups = "sdio1_0_grp";
0709 function = "sdio1";
0710 };
0711
0712 conf {
0713 groups = "sdio1_0_grp";
0714 slew-rate = <SLEW_RATE_SLOW>;
0715 power-source = <IO_STANDARD_LVCMOS18>;
0716 bias-disable;
0717 };
0718
0719 mux-cd {
0720 groups = "sdio1_cd_0_grp";
0721 function = "sdio1_cd";
0722 };
0723
0724 conf-cd {
0725 groups = "sdio1_cd_0_grp";
0726 bias-high-impedance;
0727 bias-pull-up;
0728 slew-rate = <SLEW_RATE_SLOW>;
0729 power-source = <IO_STANDARD_LVCMOS18>;
0730 };
0731 };
0732
0733 pinctrl_gpio_default: gpio-default {
0734 mux {
0735 function = "gpio0";
0736 groups = "gpio0_22_grp", "gpio0_23_grp";
0737 };
0738
0739 conf {
0740 groups = "gpio0_22_grp", "gpio0_23_grp";
0741 slew-rate = <SLEW_RATE_SLOW>;
0742 power-source = <IO_STANDARD_LVCMOS18>;
0743 };
0744
0745 mux-msp {
0746 function = "gpio0";
0747 groups = "gpio0_13_grp", "gpio0_38_grp";
0748 };
0749
0750 conf-msp {
0751 groups = "gpio0_13_grp", "gpio0_38_grp";
0752 slew-rate = <SLEW_RATE_SLOW>;
0753 power-source = <IO_STANDARD_LVCMOS18>;
0754 };
0755
0756 conf-pull-up {
0757 pins = "MIO22";
0758 bias-pull-up;
0759 };
0760
0761 conf-pull-none {
0762 pins = "MIO13", "MIO23", "MIO38";
0763 bias-disable;
0764 };
0765 };
0766 };
0767
0768 &psgtr {
0769 status = "okay";
0770 /* nc, dp, usb3, sata */
0771 clocks = <&si5341 0 0>, <&si5341 0 2>, <&si5341 0 3>;
0772 clock-names = "ref1", "ref2", "ref3";
0773 };
0774
0775 &qspi {
0776 status = "okay";
0777 flash@0 {
0778 compatible = "m25p80", "jedec,spi-nor"; /* 16MB + 16MB */
0779 #address-cells = <1>;
0780 #size-cells = <1>;
0781 reg = <0x0>;
0782 spi-tx-bus-width = <1>;
0783 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
0784 spi-max-frequency = <108000000>; /* Based on DC1 spec */
0785 };
0786 };
0787
0788 &rtc {
0789 status = "okay";
0790 };
0791
0792 &sata {
0793 status = "okay";
0794 /* SATA OOB timing settings */
0795 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
0796 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
0797 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
0798 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
0799 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
0800 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
0801 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
0802 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
0803 phy-names = "sata-phy";
0804 phys = <&psgtr 3 PHY_TYPE_SATA 1 3>;
0805 };
0806
0807 /* SD1 with level shifter */
0808 &sdhci1 {
0809 status = "okay";
0810 pinctrl-names = "default";
0811 pinctrl-0 = <&pinctrl_sdhci1_default>;
0812 disable-wp;
0813 /*
0814 * This property should be removed for supporting UHS mode
0815 */
0816 no-1-8-v;
0817 xlnx,mio-bank = <1>;
0818 };
0819
0820 &uart0 {
0821 status = "okay";
0822 pinctrl-names = "default";
0823 pinctrl-0 = <&pinctrl_uart0_default>;
0824 };
0825
0826 /* ULPI SMSC USB3320 */
0827 &usb0 {
0828 status = "okay";
0829 pinctrl-names = "default";
0830 pinctrl-0 = <&pinctrl_usb0_default>;
0831 phy-names = "usb3-phy";
0832 phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
0833 };
0834
0835 &dwc3_0 {
0836 status = "okay";
0837 dr_mode = "host";
0838 snps,usb3_lpm_capable;
0839 maximum-speed = "super-speed";
0840 };
0841
0842 &zynqmp_dpdma {
0843 status = "okay";
0844 };
0845
0846 &zynqmp_dpsub {
0847 status = "okay";
0848 phy-names = "dp-phy0", "dp-phy1";
0849 phys = <&psgtr 1 PHY_TYPE_DP 0 1>,
0850 <&psgtr 0 PHY_TYPE_DP 1 1>;
0851 };
