0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003 * dts file for Xilinx ZynqMP ZCU106
0004 *
0005 * (C) Copyright 2016 - 2021, Xilinx, Inc.
0006 *
0007 * Michal Simek <michal.simek@xilinx.com>
0008 */
0009
0010 /dts-v1/;
0011
0012 #include "zynqmp.dtsi"
0013 #include "zynqmp-clk-ccf.dtsi"
0014 #include <dt-bindings/input/input.h>
0015 #include <dt-bindings/gpio/gpio.h>
0016 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
0017 #include <dt-bindings/phy/phy.h>
0018
0019 / {
0020 model = "ZynqMP ZCU106 RevA";
0021 compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp";
0022
0023 aliases {
0024 ethernet0 = &gem3;
0025 i2c0 = &i2c0;
0026 i2c1 = &i2c1;
0027 mmc0 = &sdhci1;
0028 nvmem0 = &eeprom;
0029 rtc0 = &rtc;
0030 serial0 = &uart0;
0031 serial1 = &uart1;
0032 serial2 = &dcc;
0033 spi0 = &qspi;
0034 usb0 = &usb0;
0035 };
0036
0037 chosen {
0038 bootargs = "earlycon";
0039 stdout-path = "serial0:115200n8";
0040 };
0041
0042 memory@0 {
0043 device_type = "memory";
0044 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
0045 };
0046
0047 gpio-keys {
0048 compatible = "gpio-keys";
0049 autorepeat;
0050 switch-19 {
0051 label = "sw19";
0052 gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
0053 linux,code = <KEY_DOWN>;
0054 wakeup-source;
0055 autorepeat;
0056 };
0057 };
0058
0059 leds {
0060 compatible = "gpio-leds";
0061 heartbeat-led {
0062 label = "heartbeat";
0063 gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
0064 linux,default-trigger = "heartbeat";
0065 };
0066 };
0067
0068 ina226-u76 {
0069 compatible = "iio-hwmon";
0070 io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;
0071 };
0072 ina226-u77 {
0073 compatible = "iio-hwmon";
0074 io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
0075 };
0076 ina226-u78 {
0077 compatible = "iio-hwmon";
0078 io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;
0079 };
0080 ina226-u87 {
0081 compatible = "iio-hwmon";
0082 io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;
0083 };
0084 ina226-u85 {
0085 compatible = "iio-hwmon";
0086 io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;
0087 };
0088 ina226-u86 {
0089 compatible = "iio-hwmon";
0090 io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;
0091 };
0092 ina226-u93 {
0093 compatible = "iio-hwmon";
0094 io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;
0095 };
0096 ina226-u88 {
0097 compatible = "iio-hwmon";
0098 io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;
0099 };
0100 ina226-u15 {
0101 compatible = "iio-hwmon";
0102 io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;
0103 };
0104 ina226-u92 {
0105 compatible = "iio-hwmon";
0106 io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;
0107 };
0108 ina226-u79 {
0109 compatible = "iio-hwmon";
0110 io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
0111 };
0112 ina226-u81 {
0113 compatible = "iio-hwmon";
0114 io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;
0115 };
0116 ina226-u80 {
0117 compatible = "iio-hwmon";
0118 io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;
0119 };
0120 ina226-u84 {
0121 compatible = "iio-hwmon";
0122 io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;
0123 };
0124 ina226-u16 {
0125 compatible = "iio-hwmon";
0126 io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;
0127 };
0128 ina226-u65 {
0129 compatible = "iio-hwmon";
0130 io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
0131 };
0132 ina226-u74 {
0133 compatible = "iio-hwmon";
0134 io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;
0135 };
0136 ina226-u75 {
0137 compatible = "iio-hwmon";
0138 io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
0139 };
0140
0141 /* 48MHz reference crystal */
0142 ref48: ref48M {
0143 compatible = "fixed-clock";
0144 #clock-cells = <0>;
0145 clock-frequency = <48000000>;
0146 };
0147
0148 refhdmi: refhdmi {
0149 compatible = "fixed-clock";
0150 #clock-cells = <0>;
0151 clock-frequency = <114285000>;
0152 };
0153 };
0154
0155 &can1 {
0156 status = "okay";
0157 pinctrl-names = "default";
0158 pinctrl-0 = <&pinctrl_can1_default>;
0159 };
0160
0161 &dcc {
0162 status = "okay";
0163 };
0164
0165 &fpd_dma_chan1 {
0166 status = "okay";
0167 };
0168
0169 &fpd_dma_chan2 {
0170 status = "okay";
0171 };
0172
0173 &fpd_dma_chan3 {
0174 status = "okay";
0175 };
0176
0177 &fpd_dma_chan4 {
0178 status = "okay";
0179 };
0180
0181 &fpd_dma_chan5 {
0182 status = "okay";
0183 };
0184
0185 &fpd_dma_chan6 {
0186 status = "okay";
0187 };
0188
0189 &fpd_dma_chan7 {
0190 status = "okay";
0191 };
0192
0193 &fpd_dma_chan8 {
0194 status = "okay";
0195 };
0196
0197 &gem3 {
0198 status = "okay";
0199 phy-handle = <&phy0>;
0200 phy-mode = "rgmii-id";
0201 pinctrl-names = "default";
0202 pinctrl-0 = <&pinctrl_gem3_default>;
0203 phy0: ethernet-phy@c {
0204 reg = <0xc>;
0205 ti,rx-internal-delay = <0x8>;
0206 ti,tx-internal-delay = <0xa>;
0207 ti,fifo-depth = <0x1>;
0208 ti,dp83867-rxctrl-strap-quirk;
0209 };
0210 };
0211
0212 &gpio {
0213 status = "okay";
0214 pinctrl-names = "default";
0215 pinctrl-0 = <&pinctrl_gpio_default>;
0216 };
0217
0218 &i2c0 {
0219 status = "okay";
0220 clock-frequency = <400000>;
0221 pinctrl-names = "default", "gpio";
0222 pinctrl-0 = <&pinctrl_i2c0_default>;
0223 pinctrl-1 = <&pinctrl_i2c0_gpio>;
0224 scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
0225 sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
0226
0227 tca6416_u97: gpio@20 {
0228 compatible = "ti,tca6416";
0229 reg = <0x20>;
0230 gpio-controller; /* interrupt not connected */
0231 #gpio-cells = <2>;
0232 /*
0233 * IRQ not connected
0234 * Lines:
0235 * 0 - SFP_SI5328_INT_ALM
0236 * 1 - HDMI_SI5328_INT_ALM
0237 * 5 - IIC_MUX_RESET_B
0238 * 6 - GEM3_EXP_RESET_B
0239 * 10 - FMC_HPC0_PRSNT_M2C_B
0240 * 11 - FMC_HPC1_PRSNT_M2C_B
0241 * 2-4, 7, 12-17 - not connected
0242 */
0243 };
0244
0245 tca6416_u61: gpio@21 {
0246 compatible = "ti,tca6416";
0247 reg = <0x21>;
0248 gpio-controller;
0249 #gpio-cells = <2>;
0250 /*
0251 * IRQ not connected
0252 * Lines:
0253 * 0 - VCCPSPLL_EN
0254 * 1 - MGTRAVCC_EN
0255 * 2 - MGTRAVTT_EN
0256 * 3 - VCCPSDDRPLL_EN
0257 * 4 - MIO26_PMU_INPUT_LS
0258 * 5 - PL_PMBUS_ALERT
0259 * 6 - PS_PMBUS_ALERT
0260 * 7 - MAXIM_PMBUS_ALERT
0261 * 10 - PL_DDR4_VTERM_EN
0262 * 11 - PL_DDR4_VPP_2V5_EN
0263 * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
0264 * 13 - PS_DIMM_SUSPEND_EN
0265 * 14 - PS_DDR4_VTERM_EN
0266 * 15 - PS_DDR4_VPP_2V5_EN
0267 * 16 - 17 - not connected
0268 */
0269 };
0270
0271 i2c-mux@75 { /* u60 */
0272 compatible = "nxp,pca9544";
0273 #address-cells = <1>;
0274 #size-cells = <0>;
0275 reg = <0x75>;
0276 i2c@0 {
0277 #address-cells = <1>;
0278 #size-cells = <0>;
0279 reg = <0>;
0280 /* PS_PMBUS */
0281 u76: ina226@40 { /* u76 */
0282 compatible = "ti,ina226";
0283 #io-channel-cells = <1>;
0284 label = "ina226-u76";
0285 reg = <0x40>;
0286 shunt-resistor = <5000>;
0287 };
0288 u77: ina226@41 { /* u77 */
0289 compatible = "ti,ina226";
0290 #io-channel-cells = <1>;
0291 label = "ina226-u77";
0292 reg = <0x41>;
0293 shunt-resistor = <5000>;
0294 };
0295 u78: ina226@42 { /* u78 */
0296 compatible = "ti,ina226";
0297 #io-channel-cells = <1>;
0298 label = "ina226-u78";
0299 reg = <0x42>;
0300 shunt-resistor = <5000>;
0301 };
0302 u87: ina226@43 { /* u87 */
0303 compatible = "ti,ina226";
0304 #io-channel-cells = <1>;
0305 label = "ina226-u87";
0306 reg = <0x43>;
0307 shunt-resistor = <5000>;
0308 };
0309 u85: ina226@44 { /* u85 */
0310 compatible = "ti,ina226";
0311 #io-channel-cells = <1>;
0312 label = "ina226-u85";
0313 reg = <0x44>;
0314 shunt-resistor = <5000>;
0315 };
0316 u86: ina226@45 { /* u86 */
0317 compatible = "ti,ina226";
0318 #io-channel-cells = <1>;
0319 label = "ina226-u86";
0320 reg = <0x45>;
0321 shunt-resistor = <5000>;
0322 };
0323 u93: ina226@46 { /* u93 */
0324 compatible = "ti,ina226";
0325 #io-channel-cells = <1>;
0326 label = "ina226-u93";
0327 reg = <0x46>;
0328 shunt-resistor = <5000>;
0329 };
0330 u88: ina226@47 { /* u88 */
0331 compatible = "ti,ina226";
0332 #io-channel-cells = <1>;
0333 label = "ina226-u88";
0334 reg = <0x47>;
0335 shunt-resistor = <5000>;
0336 };
0337 u15: ina226@4a { /* u15 */
0338 compatible = "ti,ina226";
0339 #io-channel-cells = <1>;
0340 label = "ina226-u15";
0341 reg = <0x4a>;
0342 shunt-resistor = <5000>;
0343 };
0344 u92: ina226@4b { /* u92 */
0345 compatible = "ti,ina226";
0346 #io-channel-cells = <1>;
0347 label = "ina226-u92";
0348 reg = <0x4b>;
0349 shunt-resistor = <5000>;
0350 };
0351 };
0352 i2c@1 {
0353 #address-cells = <1>;
0354 #size-cells = <0>;
0355 reg = <1>;
0356 /* PL_PMBUS */
0357 u79: ina226@40 { /* u79 */
0358 compatible = "ti,ina226";
0359 #io-channel-cells = <1>;
0360 label = "ina226-u79";
0361 reg = <0x40>;
0362 shunt-resistor = <2000>;
0363 };
0364 u81: ina226@41 { /* u81 */
0365 compatible = "ti,ina226";
0366 #io-channel-cells = <1>;
0367 label = "ina226-u81";
0368 reg = <0x41>;
0369 shunt-resistor = <5000>;
0370 };
0371 u80: ina226@42 { /* u80 */
0372 compatible = "ti,ina226";
0373 #io-channel-cells = <1>;
0374 label = "ina226-u80";
0375 reg = <0x42>;
0376 shunt-resistor = <5000>;
0377 };
0378 u84: ina226@43 { /* u84 */
0379 compatible = "ti,ina226";
0380 #io-channel-cells = <1>;
0381 label = "ina226-u84";
0382 reg = <0x43>;
0383 shunt-resistor = <5000>;
0384 };
0385 u16: ina226@44 { /* u16 */
0386 compatible = "ti,ina226";
0387 #io-channel-cells = <1>;
0388 label = "ina226-u16";
0389 reg = <0x44>;
0390 shunt-resistor = <5000>;
0391 };
0392 u65: ina226@45 { /* u65 */
0393 compatible = "ti,ina226";
0394 #io-channel-cells = <1>;
0395 label = "ina226-u65";
0396 reg = <0x45>;
0397 shunt-resistor = <5000>;
0398 };
0399 u74: ina226@46 { /* u74 */
0400 compatible = "ti,ina226";
0401 #io-channel-cells = <1>;
0402 label = "ina226-u74";
0403 reg = <0x46>;
0404 shunt-resistor = <5000>;
0405 };
0406 u75: ina226@47 { /* u75 */
0407 compatible = "ti,ina226";
0408 #io-channel-cells = <1>;
0409 label = "ina226-u75";
0410 reg = <0x47>;
0411 shunt-resistor = <5000>;
0412 };
0413 };
0414 i2c@2 {
0415 #address-cells = <1>;
0416 #size-cells = <0>;
0417 reg = <2>;
0418 /* MAXIM_PMBUS - 00 */
0419 max15301@a { /* u46 */
0420 compatible = "maxim,max15301";
0421 reg = <0xa>;
0422 };
0423 max15303@b { /* u4 */
0424 compatible = "maxim,max15303";
0425 reg = <0xb>;
0426 };
0427 max15303@10 { /* u13 */
0428 compatible = "maxim,max15303";
0429 reg = <0x10>;
0430 };
0431 max15301@13 { /* u47 */
0432 compatible = "maxim,max15301";
0433 reg = <0x13>;
0434 };
0435 max15303@14 { /* u7 */
0436 compatible = "maxim,max15303";
0437 reg = <0x14>;
0438 };
0439 max15303@15 { /* u6 */
0440 compatible = "maxim,max15303";
0441 reg = <0x15>;
0442 };
0443 max15303@16 { /* u10 */
0444 compatible = "maxim,max15303";
0445 reg = <0x16>;
0446 };
0447 max15303@17 { /* u9 */
0448 compatible = "maxim,max15303";
0449 reg = <0x17>;
0450 };
0451 max15301@18 { /* u63 */
0452 compatible = "maxim,max15301";
0453 reg = <0x18>;
0454 };
0455 max15303@1a { /* u49 */
0456 compatible = "maxim,max15303";
0457 reg = <0x1a>;
0458 };
0459 max15303@1b { /* u8 */
0460 compatible = "maxim,max15303";
0461 reg = <0x1b>;
0462 };
0463 max15303@1d { /* u18 */
0464 compatible = "maxim,max15303";
0465 reg = <0x1d>;
0466 };
0467
0468 max20751@72 { /* u95 */
0469 compatible = "maxim,max20751";
0470 reg = <0x72>;
0471 };
0472 max20751@73 { /* u96 */
0473 compatible = "maxim,max20751";
0474 reg = <0x73>;
0475 };
0476 };
0477 /* Bus 3 is not connected */
0478 };
0479 };
0480
0481 &i2c1 {
0482 status = "okay";
0483 clock-frequency = <400000>;
0484 pinctrl-names = "default", "gpio";
0485 pinctrl-0 = <&pinctrl_i2c1_default>;
0486 pinctrl-1 = <&pinctrl_i2c1_gpio>;
0487 scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
0488 sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
0489
0490 /* PL i2c via PCA9306 - u45 */
0491 i2c-mux@74 { /* u34 */
0492 compatible = "nxp,pca9548";
0493 #address-cells = <1>;
0494 #size-cells = <0>;
0495 reg = <0x74>;
0496 i2c@0 {
0497 #address-cells = <1>;
0498 #size-cells = <0>;
0499 reg = <0>;
0500 /*
0501 * IIC_EEPROM 1kB memory which uses 256B blocks
0502 * where every block has different address.
0503 * 0 - 256B address 0x54
0504 * 256B - 512B address 0x55
0505 * 512B - 768B address 0x56
0506 * 768B - 1024B address 0x57
0507 */
0508 eeprom: eeprom@54 { /* u23 */
0509 compatible = "atmel,24c08";
0510 reg = <0x54>;
0511 };
0512 };
0513 i2c@1 {
0514 #address-cells = <1>;
0515 #size-cells = <0>;
0516 reg = <1>;
0517 si5341: clock-generator@36 { /* SI5341 - u69 */
0518 compatible = "silabs,si5341";
0519 reg = <0x36>;
0520 #clock-cells = <2>;
0521 #address-cells = <1>;
0522 #size-cells = <0>;
0523 clocks = <&ref48>;
0524 clock-names = "xtal";
0525 clock-output-names = "si5341";
0526
0527 si5341_0: out@0 {
0528 /* refclk0 for PS-GT, used for DP */
0529 reg = <0>;
0530 always-on;
0531 };
0532 si5341_2: out@2 {
0533 /* refclk2 for PS-GT, used for USB3 */
0534 reg = <2>;
0535 always-on;
0536 };
0537 si5341_3: out@3 {
0538 /* refclk3 for PS-GT, used for SATA */
0539 reg = <3>;
0540 always-on;
0541 };
0542 si5341_6: out@6 {
0543 /* refclk6 PL CLK125 */
0544 reg = <6>;
0545 always-on;
0546 };
0547 si5341_7: out@7 {
0548 /* refclk7 PL CLK74 */
0549 reg = <7>;
0550 always-on;
0551 };
0552 si5341_9: out@9 {
0553 /* refclk9 used for PS_REF_CLK 33.3 MHz */
0554 reg = <9>;
0555 always-on;
0556 };
0557 };
0558
0559 };
0560 i2c@2 {
0561 #address-cells = <1>;
0562 #size-cells = <0>;
0563 reg = <2>;
0564 si570_1: clock-generator@5d { /* USER SI570 - u42 */
0565 #clock-cells = <0>;
0566 compatible = "silabs,si570";
0567 reg = <0x5d>;
0568 temperature-stability = <50>;
0569 factory-fout = <300000000>;
0570 clock-frequency = <300000000>;
0571 clock-output-names = "si570_user";
0572 };
0573 };
0574 i2c@3 {
0575 #address-cells = <1>;
0576 #size-cells = <0>;
0577 reg = <3>;
0578 si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
0579 #clock-cells = <0>;
0580 compatible = "silabs,si570";
0581 reg = <0x5d>;
0582 temperature-stability = <50>; /* copy from zc702 */
0583 factory-fout = <156250000>;
0584 clock-frequency = <148500000>;
0585 clock-output-names = "si570_mgt";
0586 };
0587 };
0588 i2c@4 {
0589 #address-cells = <1>;
0590 #size-cells = <0>;
0591 reg = <4>;
0592 /* SI5328 - u20 */
0593 };
0594 i2c@5 {
0595 #address-cells = <1>;
0596 #size-cells = <0>;
0597 reg = <5>; /* FAN controller */
0598 temp@4c {/* lm96163 - u128 */
0599 compatible = "national,lm96163";
0600 reg = <0x4c>;
0601 };
0602 };
0603 /* 6 - 7 unconnected */
0604 };
0605
0606 i2c-mux@75 {
0607 compatible = "nxp,pca9548"; /* u135 */
0608 #address-cells = <1>;
0609 #size-cells = <0>;
0610 reg = <0x75>;
0611
0612 i2c@0 {
0613 #address-cells = <1>;
0614 #size-cells = <0>;
0615 reg = <0>;
0616 /* HPC0_IIC */
0617 };
0618 i2c@1 {
0619 #address-cells = <1>;
0620 #size-cells = <0>;
0621 reg = <1>;
0622 /* HPC1_IIC */
0623 };
0624 i2c@2 {
0625 #address-cells = <1>;
0626 #size-cells = <0>;
0627 reg = <2>;
0628 /* SYSMON */
0629 };
0630 i2c@3 {
0631 #address-cells = <1>;
0632 #size-cells = <0>;
0633 reg = <3>;
0634 /* DDR4 SODIMM */
0635 };
0636 i2c@4 {
0637 #address-cells = <1>;
0638 #size-cells = <0>;
0639 reg = <4>;
0640 /* SEP 3 */
0641 };
0642 i2c@5 {
0643 #address-cells = <1>;
0644 #size-cells = <0>;
0645 reg = <5>;
0646 /* SEP 2 */
0647 };
0648 i2c@6 {
0649 #address-cells = <1>;
0650 #size-cells = <0>;
0651 reg = <6>;
0652 /* SEP 1 */
0653 };
0654 i2c@7 {
0655 #address-cells = <1>;
0656 #size-cells = <0>;
0657 reg = <7>;
0658 /* SEP 0 */
0659 };
0660 };
0661 };
0662
0663 &pinctrl0 {
0664 status = "okay";
0665 pinctrl_i2c0_default: i2c0-default {
0666 mux {
0667 groups = "i2c0_3_grp";
0668 function = "i2c0";
0669 };
0670
0671 conf {
0672 groups = "i2c0_3_grp";
0673 bias-pull-up;
0674 slew-rate = <SLEW_RATE_SLOW>;
0675 power-source = <IO_STANDARD_LVCMOS18>;
0676 };
0677 };
0678
0679 pinctrl_i2c0_gpio: i2c0-gpio {
0680 mux {
0681 groups = "gpio0_14_grp", "gpio0_15_grp";
0682 function = "gpio0";
0683 };
0684
0685 conf {
0686 groups = "gpio0_14_grp", "gpio0_15_grp";
0687 slew-rate = <SLEW_RATE_SLOW>;
0688 power-source = <IO_STANDARD_LVCMOS18>;
0689 };
0690 };
0691
0692 pinctrl_i2c1_default: i2c1-default {
0693 mux {
0694 groups = "i2c1_4_grp";
0695 function = "i2c1";
0696 };
0697
0698 conf {
0699 groups = "i2c1_4_grp";
0700 bias-pull-up;
0701 slew-rate = <SLEW_RATE_SLOW>;
0702 power-source = <IO_STANDARD_LVCMOS18>;
0703 };
0704 };
0705
0706 pinctrl_i2c1_gpio: i2c1-gpio {
0707 mux {
0708 groups = "gpio0_16_grp", "gpio0_17_grp";
0709 function = "gpio0";
0710 };
0711
0712 conf {
0713 groups = "gpio0_16_grp", "gpio0_17_grp";
0714 slew-rate = <SLEW_RATE_SLOW>;
0715 power-source = <IO_STANDARD_LVCMOS18>;
0716 };
0717 };
0718
0719 pinctrl_uart0_default: uart0-default {
0720 mux {
0721 groups = "uart0_4_grp";
0722 function = "uart0";
0723 };
0724
0725 conf {
0726 groups = "uart0_4_grp";
0727 slew-rate = <SLEW_RATE_SLOW>;
0728 power-source = <IO_STANDARD_LVCMOS18>;
0729 };
0730
0731 conf-rx {
0732 pins = "MIO18";
0733 bias-high-impedance;
0734 };
0735
0736 conf-tx {
0737 pins = "MIO19";
0738 bias-disable;
0739 };
0740 };
0741
0742 pinctrl_uart1_default: uart1-default {
0743 mux {
0744 groups = "uart1_5_grp";
0745 function = "uart1";
0746 };
0747
0748 conf {
0749 groups = "uart1_5_grp";
0750 slew-rate = <SLEW_RATE_SLOW>;
0751 power-source = <IO_STANDARD_LVCMOS18>;
0752 };
0753
0754 conf-rx {
0755 pins = "MIO21";
0756 bias-high-impedance;
0757 };
0758
0759 conf-tx {
0760 pins = "MIO20";
0761 bias-disable;
0762 };
0763 };
0764
0765 pinctrl_usb0_default: usb0-default {
0766 mux {
0767 groups = "usb0_0_grp";
0768 function = "usb0";
0769 };
0770
0771 conf {
0772 groups = "usb0_0_grp";
0773 slew-rate = <SLEW_RATE_SLOW>;
0774 power-source = <IO_STANDARD_LVCMOS18>;
0775 };
0776
0777 conf-rx {
0778 pins = "MIO52", "MIO53", "MIO55";
0779 bias-high-impedance;
0780 };
0781
0782 conf-tx {
0783 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
0784 "MIO60", "MIO61", "MIO62", "MIO63";
0785 bias-disable;
0786 };
0787 };
0788
0789 pinctrl_gem3_default: gem3-default {
0790 mux {
0791 function = "ethernet3";
0792 groups = "ethernet3_0_grp";
0793 };
0794
0795 conf {
0796 groups = "ethernet3_0_grp";
0797 slew-rate = <SLEW_RATE_SLOW>;
0798 power-source = <IO_STANDARD_LVCMOS18>;
0799 };
0800
0801 conf-rx {
0802 pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
0803 "MIO75";
0804 bias-high-impedance;
0805 low-power-disable;
0806 };
0807
0808 conf-tx {
0809 pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
0810 "MIO69";
0811 bias-disable;
0812 low-power-enable;
0813 };
0814
0815 mux-mdio {
0816 function = "mdio3";
0817 groups = "mdio3_0_grp";
0818 };
0819
0820 conf-mdio {
0821 groups = "mdio3_0_grp";
0822 slew-rate = <SLEW_RATE_SLOW>;
0823 power-source = <IO_STANDARD_LVCMOS18>;
0824 bias-disable;
0825 };
0826 };
0827
0828 pinctrl_can1_default: can1-default {
0829 mux {
0830 function = "can1";
0831 groups = "can1_6_grp";
0832 };
0833
0834 conf {
0835 groups = "can1_6_grp";
0836 slew-rate = <SLEW_RATE_SLOW>;
0837 power-source = <IO_STANDARD_LVCMOS18>;
0838 };
0839
0840 conf-rx {
0841 pins = "MIO25";
0842 bias-high-impedance;
0843 };
0844
0845 conf-tx {
0846 pins = "MIO24";
0847 bias-disable;
0848 };
0849 };
0850
0851 pinctrl_sdhci1_default: sdhci1-default {
0852 mux {
0853 groups = "sdio1_0_grp";
0854 function = "sdio1";
0855 };
0856
0857 conf {
0858 groups = "sdio1_0_grp";
0859 slew-rate = <SLEW_RATE_SLOW>;
0860 power-source = <IO_STANDARD_LVCMOS18>;
0861 bias-disable;
0862 };
0863
0864 mux-cd {
0865 groups = "sdio1_cd_0_grp";
0866 function = "sdio1_cd";
0867 };
0868
0869 conf-cd {
0870 groups = "sdio1_cd_0_grp";
0871 bias-high-impedance;
0872 bias-pull-up;
0873 slew-rate = <SLEW_RATE_SLOW>;
0874 power-source = <IO_STANDARD_LVCMOS18>;
0875 };
0876
0877 mux-wp {
0878 groups = "sdio1_wp_0_grp";
0879 function = "sdio1_wp";
0880 };
0881
0882 conf-wp {
0883 groups = "sdio1_wp_0_grp";
0884 bias-high-impedance;
0885 bias-pull-up;
0886 slew-rate = <SLEW_RATE_SLOW>;
0887 power-source = <IO_STANDARD_LVCMOS18>;
0888 };
0889 };
0890
0891 pinctrl_gpio_default: gpio-default {
0892 mux {
0893 function = "gpio0";
0894 groups = "gpio0_22_grp", "gpio0_23_grp";
0895 };
0896
0897 conf {
0898 groups = "gpio0_22_grp", "gpio0_23_grp";
0899 slew-rate = <SLEW_RATE_SLOW>;
0900 power-source = <IO_STANDARD_LVCMOS18>;
0901 };
0902
0903 mux-msp {
0904 function = "gpio0";
0905 groups = "gpio0_13_grp", "gpio0_38_grp";
0906 };
0907
0908 conf-msp {
0909 groups = "gpio0_13_grp", "gpio0_38_grp";
0910 slew-rate = <SLEW_RATE_SLOW>;
0911 power-source = <IO_STANDARD_LVCMOS18>;
0912 };
0913
0914 conf-pull-up {
0915 pins = "MIO22";
0916 bias-pull-up;
0917 };
0918
0919 conf-pull-none {
0920 pins = "MIO13", "MIO23", "MIO38";
0921 bias-disable;
0922 };
0923 };
0924 };
0925
0926 &psgtr {
0927 status = "okay";
0928 /* nc, sata, usb3, dp */
0929 clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
0930 clock-names = "ref1", "ref2", "ref3";
0931 };
0932
0933 &qspi {
0934 status = "okay";
0935 flash@0 {
0936 compatible = "m25p80", "jedec,spi-nor"; /* 16MB + 16MB */
0937 #address-cells = <1>;
0938 #size-cells = <1>;
0939 reg = <0x0>;
0940 spi-tx-bus-width = <1>;
0941 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
0942 spi-max-frequency = <108000000>; /* Based on DC1 spec */
0943 };
0944 };
0945
0946 &rtc {
0947 status = "okay";
0948 };
0949
0950 &sata {
0951 status = "okay";
0952 /* SATA OOB timing settings */
0953 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
0954 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
0955 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
0956 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
0957 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
0958 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
0959 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
0960 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
0961 phy-names = "sata-phy";
0962 phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
0963 };
0964
0965 /* SD1 with level shifter */
0966 &sdhci1 {
0967 status = "okay";
0968 /*
0969 * This property should be removed for supporting UHS mode
0970 */
0971 no-1-8-v;
0972 pinctrl-names = "default";
0973 pinctrl-0 = <&pinctrl_sdhci1_default>;
0974 xlnx,mio-bank = <1>;
0975 };
0976
0977 &uart0 {
0978 status = "okay";
0979 pinctrl-names = "default";
0980 pinctrl-0 = <&pinctrl_uart0_default>;
0981 };
0982
0983 &uart1 {
0984 status = "okay";
0985 pinctrl-names = "default";
0986 pinctrl-0 = <&pinctrl_uart1_default>;
0987 };
0988
0989 /* ULPI SMSC USB3320 */
0990 &usb0 {
0991 status = "okay";
0992 pinctrl-names = "default";
0993 pinctrl-0 = <&pinctrl_usb0_default>;
0994 phy-names = "usb3-phy";
0995 phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
0996 };
0997
0998 &dwc3_0 {
0999 status = "okay";
1000 dr_mode = "host";
1001 snps,usb3_lpm_capable;
1002 maximum-speed = "super-speed";
1003 };
1004
1005 &watchdog0 {
1006 status = "okay";
1007 };
1008
1009 &zynqmp_dpdma {
1010 status = "okay";
1011 };
1012
1013 &zynqmp_dpsub {
1014 status = "okay";
1015 phy-names = "dp-phy0", "dp-phy1";
1016 phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
1017 <&psgtr 0 PHY_TYPE_DP 1 3>;
1018 };
